A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 178-179

  Hsu, Steven ^a   Agarwal, Amit ^a   Anders, Mark ^a   Mathew, Sanu ^a   Kaul, Himanshu ^a   Sheikh, Farhana ^a   Krishnamurthy, Ram ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA PATHS; ENERGY EFFICIENT; HIGH ENERGY EFFICIENCY; HIGH-PERFORMANCE MICROPROCESSORS; HIGH-THROUGHPUT DATA; LARGE DATASETS; LEVEL SHIFTER; MATRIX TRANSPOSE; OPERATING RANGES; PERMUTATION OPERATIONS; PVT VARIATIONS; READ/WRITE OPERATIONS; REGISTER FILES; SUBTHRESHOLD; SUBTHRESHOLD OPERATION; SUPPLY VOLTAGES; TRANSISTOR VARIATION; TRANSMISSION GATE; ULTRA-LOW-VOLTAGE;

DELAY CIRCUITS; ENERGY EFFICIENCY; SIGNAL PROCESSING; THRESHOLD VOLTAGE;

VECTORS;

EID: 84860694155     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6176966     Document Type: Conference Paper

References (4)

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3. H.-J. Stolberg, et al., "An SoC with Two Multimedia DSPs and a RISC Core for Video Compression Applications," ISSCC Dig. Tech. Papers, pp. 330-331, 2004.
4. A. Wang, et al., "A 180mV FFT Processor Using Sub-threshold Circuits Techniques," ISSCC Dig. Tech. Papers, pp. 292-293, 2004.