Conditional push-pull pulsed latches with 726fJ-ps energy-delay product in 65nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 482-483

  Consoli, Elio ^a   Alioto, Massimo ^b,c   Palumbo, Gaetano ^a   Rabaey, Jan ^d  

^a UNIVERSITY OF CATANIA   (Italy)

^b UNIVERSITY OF SIENA   (Italy)

^c UNIVERSITY OF MICHIGAN   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

65NM CMOS TECHNOLOGY; BUILDING BLOCKES; CLOCK PERIOD; DELAY IMPROVEMENTS; DESIGN SPACES; ENERGY DELAY PRODUCT; ENERGY EFFICIENT; HIGH-SPEED; LOW POWER; MASTER-SLAVE; SPACE REGIONS; TEST CHIPS;

CMOS INTEGRATED CIRCUITS; ENERGY EFFICIENCY; ENERGY UTILIZATION; PULSE GENERATORS;

PRODUCT DESIGN;

EID: 84860655024     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6177100     Document Type: Conference Paper

References (6)

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5. N. Nedovic, et al., "A Clock Skew Absorbing Flip-Flop," ISSCC Dig. Tech. Papers, pp. 342-497, 2003.
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