메뉴 건너뛰기




Volumn , Issue , 2009, Pages 225-230

A 45nm CMOS 0.35V-optimized standard cell library for ultra-low power applications

Author keywords

Bose choudhury hocquenghem; Circuit; CMOS; Design; Energy; Library; Logic; Low power; Methodology; Subthreshold; Ultra low voltage

Indexed keywords

BOSE CHOUDHURY HOCQUENGHEM; CMOS DESIGN; LOW POWER; SUBTHRESHOLD; ULTRA-LOW-VOLTAGE;

EID: 70449707766     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1594233.1594288     Document Type: Conference Paper
Times cited : (15)

References (20)
  • 1
    • 11944273157 scopus 로고    scopus 로고
    • Wang, A.; Chandrakasan, A., A 180-mV subthreshold FFT processor using a minimum energy design methodology, Solid-State Circuits, IEEE Journal of , 40, no.1, pp. 310-319, Jan. 2005
    • Wang, A.; Chandrakasan, A., "A 180-mV subthreshold FFT processor using a minimum energy design methodology," Solid-State Circuits, IEEE Journal of , vol.40, no.1, pp. 310-319, Jan. 2005
  • 2
    • 37749025732 scopus 로고    scopus 로고
    • Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits
    • Jan
    • Verma, N.; Kwong, J.; Chandrakasan, A.P., "Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits", Electron Devices, IEEE Transactions on , vol.55, no.1, pp.163-174, Jan. 2008
    • (2008) Electron Devices, IEEE Transactions on , vol.55 , Issue.1 , pp. 163-174
    • Verma, N.1    Kwong, J.2    Chandrakasan, A.P.3
  • 10
    • 25144514874 scopus 로고    scopus 로고
    • Calhoun, B.H.; Wang, A.; Chandrakasan, A., Modeling and sizing for minimum energy operation in subthreshold circuits, Solid-State Circuits, IEEE Journal of , 40, no.9, pp. 1778-1786, Sept. 2005
    • Calhoun, B.H.; Wang, A.; Chandrakasan, A., "Modeling and sizing for minimum energy operation in subthreshold circuits," Solid-State Circuits, IEEE Journal of , vol.40, no.9, pp. 1778-1786, Sept. 2005
  • 15
    • 0024754187 scopus 로고    scopus 로고
    • Pelgrom, M.J.M.; Duinmaijer, A.C.J.; Welbers, A.P.G., Matching properties of MOS transistors, Solid-State Circuits, IEEE Journal of , 24, no.5, pp. 1433-1439, Oct 1989
    • Pelgrom, M.J.M.; Duinmaijer, A.C.J.; Welbers, A.P.G., "Matching properties of MOS transistors," Solid-State Circuits, IEEE Journal of , vol.24, no.5, pp. 1433-1439, Oct 1989
  • 18
    • 49349098019 scopus 로고    scopus 로고
    • Ultra Low Voltage Level Shifters to Interface Sub and Super Threshold Reconfigurable Logic Cells
    • 1-8 March
    • Chavan, A.; MacDonald, E., "Ultra Low Voltage Level Shifters to Interface Sub and Super Threshold Reconfigurable Logic Cells," Aerospace Conference, 2008 IEEE , pp.1-6, 1-8 March 2008
    • (2008) Aerospace Conference, 2008 IEEE , pp. 1-6
    • Chavan, A.1    MacDonald, E.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.