Timing error prevention using elastic clocking

2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011

Volumn , Issue , 2011, Pages

  Chae, Kwanyeob ^a   Lee, Chang Ho ^a   Mukhopadhyay, Saibal ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK STRETCHING; CMOS TECHNOLOGY; DYNAMIC CONTROLS; DYNAMIC TIMING; LOWER-POWER CONSUMPTION; NET EFFECT; OPERATING FREQUENCY; PERFORMANCE PENALTIES; POWER-PERFORMANCE TRADE-OFFS; SAFETY MARGIN; TARGET FREQUENCIES; TARGET POWER; TEST-CHIP; TIME BORROWING; TIMING ERRORS; TIMING SLACK; UNDER VOLTAGE;

CMOS INTEGRATED CIRCUITS; ERRORS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; LOGIC CIRCUITS; LOGIC DESIGN; PIPELINES;

TIMING CIRCUITS;

EID: 79959363610     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2011.5783192     Document Type: Conference Paper

References (13)

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