-
1
-
-
78049530441
-
-
AbsInt Angewandte Informatik GmbH
-
AbsInt Angewandte Informatik GmbH, "aiT: Worst-Case Execution Time Analyzers, " http://www.absint.com/ait, 2013.
-
(2013)
AiT: Worst-Case Execution Time Analyzers
-
-
-
2
-
-
84921411847
-
-
Malardalen WCET Research Group
-
Malardalen WCET Research Group, "WCET Benchmarks," http://www.mrtc.mdh.se/projects/wcet, 2013.
-
(2013)
WCET Benchmarks
-
-
-
3
-
-
0003681925
-
-
UTDSP Benchmark Suite, http://www.eecg.toronto.edu/-corinna/DSP/infrastructure/UTDSP.tar.gz, 2013.
-
(2013)
UTDSP Benchmark Suite
-
-
-
5
-
-
84878490262
-
Partitioning sporadic task systems upon memory-constrained multiprocessors
-
article 78
-
S. Baruah, "Partitioning Sporadic Task Systems Upon Memory-Constrained Multiprocessors," ACM Trans. Embedded Computing Systems, vol. 12, article 78, 2013.
-
(2013)
ACM Trans. Embedded Computing Systems
, vol.12
-
-
Baruah, S.1
-
7
-
-
67649890572
-
Schedulability analysis of global scheduling algorithms on multiprocessor platforms
-
Apr
-
M. Bertogna, M. Cirinei, and G. Lipar, "Schedulability Analysis of Global Scheduling Algorithms on Multiprocessor Platforms," IEEE Trans. Parallel and Distributed Systems, vol. 20, no. 4, pp. 553-566, Apr. 2009.
-
(2009)
IEEE Trans. Parallel and Distributed Systems
, vol.20
, Issue.4
, pp. 553-566
-
-
Bertogna, M.1
Cirinei, M.2
Lipar, G.3
-
8
-
-
84877745651
-
Real-time partitioned scheduling on multi-core systems with local and global memories
-
C.-W. Chang, J.-J. Chen, T.-W. Kuo, and H. Falk, "Real-Time Partitioned Scheduling on Multi-Core Systems with Local and Global Memories," Proc. 18th Asia and South Pacific Design Automation Conf. (ASP-DAC), 2013.
-
(2013)
Proc. 18th Asia and South Pacific Design Automation Conf. (ASP-DAC
-
-
Chang, C.-W.1
Chen, J.-J.2
Kuo, T.-W.3
Falk, H.4
-
9
-
-
84869014229
-
Partitioned scheduling for real-time tasks on multiprocessor embedded systems with programmable shared srams
-
C.-W. Chang, J.-J. Chen, W. Munawar, T.-W. Kuo, and H. Falk, "Partitioned Scheduling for Real-Time Tasks on Multiprocessor Embedded Systems with Programmable Shared SRAMs," Proc. ACM 10th Int'l Conf. Embedded Software (EMSOFT), 2012.
-
(2012)
Proc. ACM 10th Int'l Conf. Embedded Software (EMSOFT
-
-
Chang, C.-W.1
Chen, J.-J.2
Munawar, W.3
Kuo, T.-W.4
Falk, H.5
-
11
-
-
84894307471
-
Task set synthesis with cost minimization for sporadic real-time tasks
-
J.-J. Chen, "Task Set Synthesis with Cost Minimization for Sporadic Real-Time Tasks," Proc. IEEE Real-Time Systems Symp. (RTSS), 2013.
-
(2013)
Proc. IEEE Real-Time Systems Symp. (RTSS
-
-
Chen, J.-J.1
-
13
-
-
84866446143
-
Partitioned packing and scheduling for sporadic real-time tasks in identical multiprocessor systems
-
J.-J. Chen and S. Chakraborty, "Partitioned Packing and Scheduling for Sporadic Real-Time Tasks in Identical Multiprocessor Systems," Proc. 24th Euromicro Conf. Real-Time Systems (ECRTS), pp. 24-33, 2012.
-
(2012)
Proc. 24th Euromicro Conf. Real-Time Systems (ECRTS
, pp. 24-33
-
-
Chen, J.-J.1
Chakraborty, S.2
-
14
-
-
84887962188
-
Adaptive cache aware bi-tier work-stealing in multi-socket multi-core architectures
-
Dec
-
Q. Chen, M. Guo, and Z. Huang, "Adaptive Cache Aware Bi-Tier Work-Stealing in Multi-Socket Multi-Core Architectures," IEEE Trans. Parallel and Distributed Systems, vol. 24, no. 12, pp. 2334-2343, Dec. 2013.
-
(2013)
IEEE Trans. Parallel and Distributed Systems
, vol.24
, Issue.12
, pp. 2334-2343
-
-
Chen, Q.1
Guo, M.2
Huang, Z.3
-
15
-
-
79960204163
-
A survey of hard real-time scheduling for multiprocessor systems
-
article 35, Oct
-
R.I. Davis and A. Burns, "A Survey of Hard Real-Time Scheduling for Multiprocessor Systems," ACM Computing Surveys, vol. 43, no. 4, article 35, Oct. 2011.
-
(2011)
ACM Computing Surveys
, vol.43
, Issue.4
-
-
Davis, R.I.1
Burns, A.2
-
16
-
-
51249181640
-
Bin packing can be solved within 1+epsilon in linear time
-
W.F. de la Vega and G.S. Lueker, "Bin Packing Can Be Solved Within 1+Epsilon in Linear Time," Combinatorica, vol. 1, no. 4, pp. 349-355, 1981.
-
(1981)
Combinatorica
, vol.1
, Issue.4
, pp. 349-355
-
-
De La Vega, W.F.1
Lueker, G.S.2
-
17
-
-
84855721466
-
The tight bound of first fit decreasing bin-packing algorithm is ffdoi -11 9 op toi + 6 9
-
G. Dosa, "The Tight Bound of First Fit Decreasing Bin-Packing Algorithm is FFDoI -11 9 OP ToI + 6 9," Proc. First Int'l Conf. Combinatorics, Algorithms, Probabilistic and Experimental Methodologies, pp. 1-11, 2007.
-
(2007)
Proc. First Int'l Conf. Combinatorics, Algorithms, Probabilistic and Experimental Methodologies
, pp. 1-11
-
-
Dosa, G.1
-
21
-
-
56749174001
-
Hierarchical memory system design for a heterogeneous multi-core processor
-
J. Guo, M. Lai, Z. Pang, L. Huang, F. Chen, K. Dai, and Z. Wang "Hierarchical Memory System Design for a Heterogeneous Multi-Core Processor, Proc. ACM Symp. Applied Computing (SAC), 2008.
-
(2008)
Proc. ACM Symp. Applied Computing (SAC
-
-
Guo, J.1
Lai, M.2
Pang, Z.3
Huang, L.4
Chen, F.5
Dai, K.6
Wang, Z.7
-
22
-
-
80155187624
-
Optimal data allocation for scratch-pad memory on embedded multi-core systems
-
Y. Guo, Q. Zhuge, J. Hu, M. Qiu, and E.H.-M. Sha, "Optimal Data Allocation for Scratch-Pad Memory on Embedded Multi-Core Systems," Proc. Int'l Conf. Parallel Processing (ICPP), pp. 464-471, 2011.
-
(2011)
Proc. Int'l Conf. Parallel Processing (ICPP
, pp. 464-471
-
-
Guo, Y.1
Zhuge, Q.2
Hu, J.3
Qiu, M.4
Sha, E.H.-M.5
-
23
-
-
84880049986
-
Lvtppp: Live-time protected pseudo-partitioning of multi-core shared caches
-
Aug
-
Z. Huang, M. Zhu, and L. Xiao, "LvtPPP: Live-Time Protected Pseudo-Partitioning of Multi-Core Shared Caches," IEEE Trans. Parallel and Distributed Systems, vol. 24, no. 8, pp. 1622-1632, Aug. 2013.
-
(2013)
IEEE Trans. Parallel and Distributed Systems
, vol.24
, Issue.8
, pp. 1622-1632
-
-
Huang, Z.1
Zhu, M.2
Xiao, L.3
-
24
-
-
25844503119
-
Introduction to the cell multiprocessor
-
J.A. Kahle, M.N. Day, H.P. Hofstee, C.R. Johns, T.R. Maeurer, and D. Shippy, "Introduction to the Cell Multiprocessor," IBM J. Research and Development, vol. 49, no. 4.5, pp. 589-604, 2005.
-
(2005)
IBM J. Research and Development
, vol.49
, Issue.45
, pp. 589-604
-
-
Kahle, J.A.1
Day, M.N.2
Hofstee, H.P.3
Johns, C.R.4
Maeurer, T.R.5
Shippy, D.6
-
26
-
-
79957590650
-
Resource sharing in gpu-Accelerated windowing systems
-
S. Kato, K. Lakshmanan, Y. Ishikawa, and R. Rajkumar, "Resource Sharing in GPU-Accelerated Windowing Systems," Proc. IEEE Real-Time and Embedded Technology and Applications Symp. (RTAS), 2011.
-
(2011)
Proc. IEEE Real-Time and Embedded Technology and Applications Symp. (RTAS
-
-
Kato, S.1
Lakshmanan, K.2
Ishikawa, Y.3
Rajkumar, R.4
-
27
-
-
85077122204
-
Gdev: First-class gpu resource management in the operating system
-
S. Kato, M. McThrow, C. Maltzahn, and S. Brandt, "Gdev: First-Class GPU Resource Management in the Operating System," Proc. USENIX Conf. Ann. Technical Conf. (ATC), 2012.
-
(2012)
Proc. USENIX Conf. Ann. Technical Conf. (ATC
-
-
Kato, S.1
McThrow, M.2
Maltzahn, C.3
Brandt, S.4
-
28
-
-
70449572703
-
Semi-partitioned scheduling of sporadic task systems on multiprocessors
-
S. Kato, N. Yamasaki, and Y. Ishikawa., "Semi-Partitioned Scheduling of Sporadic Task Systems on Multiprocessors," Proc. 21st Euromicro Conf. Real-Time Systems (ECRTS), pp. 249-258, 2009.
-
(2009)
Proc. 21st Euromicro Conf. Real-Time Systems (ECRTS
, pp. 249-258
-
-
Kato, S.1
Yamasaki, N.2
Ishikawa, Y.3
-
29
-
-
80052979914
-
Bus-Aware multicore wcet analysis through tdma offset bounds
-
T. Kelter, H. Falk, P. Marwedel, S. Chattopadhyay, and A. Roychoudhury, "Bus-Aware Multicore WCET Analysis through TDMA Offset Bounds," Proc. Euromicro Conf. Real-Time Systems (ECRTS), 2011.
-
(2011)
Proc. Euromicro Conf. Real-Time Systems (ECRTS
-
-
Kelter, T.1
Falk, H.2
Marwedel, P.3
Chattopadhyay, S.4
Roychoudhury, A.5
-
31
-
-
70450227674
-
Disaggregated memory for expansion and sharing in blade servers
-
K. Lim, J. Chang, T. Mudge, P. Ranganathan, S.K. Reinhardt, and T.F. Wenisch, "Disaggregated Memory for Expansion and Sharing in Blade Servers," Proc. 36th Ann. Int'l Symp. Computer Architecture (ISCA), pp. 267-278, 2009.
-
(2009)
Proc. 36th Ann. Int'l Symp. Computer Architecture (ISCA
, pp. 267-278
-
-
Lim, K.1
Chang, J.2
Mudge, T.3
Ranganathan, P.4
Reinhardt, S.K.5
Wenisch, T.F.6
-
32
-
-
84974687699
-
Scheduling algorithms for multiprogramming in a hard-real-time environment
-
C.L. Liu and J.W. Layland, "Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment," J. ACM, vol. 20, no. 1, pp. 46-61, 1973.
-
(1973)
J. ACM
, vol.20
, Issue.1
, pp. 46-61
-
-
Liu, C.L.1
Layland, J.W.2
-
33
-
-
84881107758
-
Integrating cache related pre-emption delay analysis into edf scheduling
-
W. Lunniss, S. Altmeyer, C. Maiza, and R.I. Davis, "Integrating Cache Related Pre-Emption Delay Analysis Into Edf Scheduling," Proc. IEEE 19th Real-Time and Embedded Technology and Applications Symp. (RTAS), 2013.
-
(2013)
Proc. IEEE 19th Real-Time and Embedded Technology and Applications Symp. (RTAS
-
-
Lunniss, W.1
Altmeyer, S.2
Maiza, C.3
Davis, R.I.4
-
38
-
-
78649521961
-
Mersa: Multicore execution of hard real-time applications supporting analyzability
-
T. Ungerer, F.J. Cazorla, P. Sainrat, G. Bernat, Z. Petrov, H. Casse, C. Rochange, E. Quinones, S. Uhrig, M. Gerdes, I. Guliashvili, M. Houston, F. Kluge, S. Metzlaff, J. Mische, M. Paolieri, and J. Wolf, "Mersa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability," Micro, vol. 30, pp. 66-75, 2010.
-
(2010)
Micro
, vol.30
, pp. 66-75
-
-
Ungerer, T.1
Cazorla, F.J.2
Sainrat, P.3
Bernat, G.4
Petrov, Z.5
Casse, H.6
Rochange, C.7
Quinones, E.8
Uhrig, S.9
Gerdes, M.10
Guliashvili, I.11
Houston, M.12
Kluge, F.13
Metzlaff, S.14
Mische, J.15
Paolieri, M.16
Wolf, J.17
-
39
-
-
81455158949
-
Fast construction of sah bvhs on the intel many integrated core (mic) architecture
-
Jan
-
I. Wald, "Fast Construction of Sah Bvhs on the Intel Many Integrated Core (MIC) Architecture," IEEE Trans. Visualization and Computer Graphics, vol. 18, no. 1, pp. 47-57, Jan. 2012.
-
(2012)
IEEE Trans. Visualization and Computer Graphics
, vol.18
, Issue.1
, pp. 47-57
-
-
Wald, I.1
-
40
-
-
84874344328
-
Investigation of scratchpad memory for preemptive multitasking
-
J. Whitham, R.I. Davis, N.C. Audsley, S. Altmeyer, and C. Maiza, "Investigation of Scratchpad Memory for Preemptive Multitasking," Proc. IEEE 33rd Real-Time Systems Symp. (RTSS), 2012.
-
(2012)
Proc. IEEE 33rd Real-Time Systems Symp. (RTSS
-
-
Whitham, J.1
Davis, R.I.2
Audsley, N.C.3
Altmeyer, S.4
Maiza, C.5
-
41
-
-
0000930151
-
There is no asymptotic ptas for two-dimensional vector packing
-
G.J. Woeginger, "There is no Asymptotic PTAS for Two-Dimensional Vector Packing," Information Processing Letters, vol. 64, no. 6, pp. 293-294, 1997.
-
(1997)
Information Processing Letters
, vol.64
, Issue.6
, pp. 293-294
-
-
Woeginger, G.J.1
-
42
-
-
84921356693
-
Leveraging both data cache and scratchpad memory through synergetic data allocation
-
H. Yunz, G. Yaoz, R. Pellizzoni, M. Caccamo, and L. Sha, "Leveraging Both Data Cache and Scratchpad Memory through Synergetic Data Allocation," Proc. IEEE Real-Time and Embedded Technology and Applications Symp. (RTAS), 2013.
-
Proc. IEEE Real-Time and Embedded Technology and Applications Symp. (RTAS
, vol.2013
-
-
Yunz, H.1
Yaoz, G.2
Pellizzoni, R.3
Caccamo, M.4
Sha, L.5
-
43
-
-
0003268059
-
Dspstone: A dsp-oriented benchmarking methodology
-
V. Zivojnovic, J.M. Velarde, C. Schlager, and H. Meyr, "DSPstone: A DSP-Oriented Benchmarking Methodology," Proc. Int'l Conf. Signal Processing and Technology (ICSPAT), 1994.
-
(1994)
Proc. Int'l Conf. Signal Processing and Technology (ICSPAT
-
-
Zivojnovic, V.1
Velarde, J.M.2
Schlager, C.3
Meyr, H.4
|