Fast construction of SAH BVHs on the Intel Many Integrated Core (MIC) architecture

IEEE Transactions on Visualization and Computer Graphics

Volumn 18, Issue 1, 2012, Pages 47-57

  Wald, Ingo ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Bounding volume hierarchies (BVHs); Intel MIC architecture; parallel BVH construction; surface area heuristic (SAH)

Indexed keywords

BOUNDING VOLUME HIERARCHIES; DATA LAYOUTS; INTEGRATED CORE; KD-TREE; PARALLELIZATIONS; REGULAR GRIDS; SIMD PROCESSING; SURFACE AREA; SURFACE AREA HEURISTIC (SAH);

PROGRAM PROCESSORS;

ARCHITECTURE;

EID: 81455158949     PISSN: 10772626     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVCG.2010.251     Document Type: Article

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