Merasa: Multicore execution of hard real-time applications supporting analyzability

IEEE Micro

Volumn 30, Issue 5, 2010, Pages 66-75

  Ungerer, Theo ^a   Cazorla, Francisco ^b   Sainrat, Pascal ^c   Bernat, Guillem ^d   Petrov, Zlatko ^e   Rochange, Christine ^c   Quinones, Eduardo ^b   Gerdes, Mike ^a   Paolieri, Marco ^b   Wolf, Julian ^a   Casse, Hugues ^c   Uhrig, Sascha ^a   Guliashvili, Irakli ^a   Houston, Michael ^d   Kluge, Floria ^a   Metzlaff, Stefan ^a   Mische, Jorg ^a  

^a UNIVERSITY OF AUGSBURG   (Germany)

^b BARCELONA SUPERCOMPUTING CENTER   (Spain)

^c UNIVERSITÉ DE TOULOUSE   (France)

^d RAPITA SYSTEMS LTD   (United Kingdom)

^e Life Science Competence Centre   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

HARD REAL-TIME; HARDWARE DESIGN; MULTI CORE; MULTI-CORE PROCESSOR; MULTICORE PROCESSOR DESIGNS; SYSTEM SOFTWARES; WORST-CASE EXECUTION TIME ANALYSIS;

EMBEDDED SOFTWARE; EMBEDDED SYSTEMS;

REAL TIME SYSTEMS;

EID: 78649521961     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2010.78     Document Type: Article

References (14)

1. C. Ballabriga et al., "Otawa: an Open Toolbox for Adaptive WCET Analysis" IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS), Springer, 2010, pp. 35-46.
2. "RapiTime White Paper", Rapita Systems, 2008, http://www.rapitasystems.com/system/files/RapiTime-WhitePaper.pdf.
3. A. Bonenfant et al., Coding Guidelines for WCET Analysis Using Measurement-based and Static Analysis Techniques, tech. report RIT/RR-2010-8-FR, Institut de Recherche en Informatique de Toulouse, Universite Paul Sabatier, 2010; ftp://ftp.irit.fr/IRIT/TRACES/IRIT-RR-2010-8-FR.pdf.
4. J. Mische et al., "How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT", Proc. 23rd Int'l Conf. Architecture of Computing Systems (ARCS 10), Springer-Verlag, 2010, pp. 2-14
5. TriCore 1 User's Manual, v. 1.3.8, Infineon Technologies, 2008.
6. J. Mische et al., "Exploiting Spare Resources of In-order SMT Processors Executing Hard Real-time Threads", Proc. IEEE Int'l Conf. Computer Design (ICCD 08), IEEE CS Press, 2008, pp. 371-376.
7. S. Metzlaff et al., "Predictable Dynamic nstruction Scratchpad for Simultaneous Multithreaded Processors", Proc. 9th Workshop Memory Performance (Medea 08), ACM Press, 2008, pp. 38-45.
8. M. Paolieri et al., "Hardware Support for WCET Analysis of Hard Real-Time Multicore Systems", Proc. 36th Int'l Symp. Computer Architecture (ISCA 09), ACM Press, 2009, pp. 57-68.
9. M. Paolieri et al., "An Analyzable Memory Controller for Hard Real-Time CMPs", Embedded Systems Letters, vol. 1, no. 4, Dec. 2009, pp. 86-90.
10. J. Wolf et al., "RTOS Support for Parallel Execution of Hard Real-Time Applications on the Merasa Multicore Processor", Proc. 13th IEEE Int'l Symp. Object/Component/Serviceoriented Real-time Distributed Computing (ISORC 10), IEEE CS Press, 2010, pp. 193-201.
11. M. de Michiel et al., "Static Loop Bound Analysis of C Programs Based on Flow Analysis and Abstract Interpretation", Proc. IEEE Int'l Conf. Embedded and Real-Time Computing Systems and Applications (RTCSA 08), IEEE CS Press, 2008, pp. 161-166.
12. C. Rochange and P. Sainrat, "A Context-Parameterized Model for Static Analysis of Execution Times", Trans. High-Performance Embedded Architectures and Compilers (HiPEAC), vol. 2, no. 3, Springer-Verlag, 2007, pp. 109-128.
13. Y.-T. S. Li and S. Malik, "Performance Analysis of Embedded Software using Implicit Path Enumeration", Proc. Workshop Languages, Compilers, and Tools for Realtime Systems, ACM Press, 1995, pp. 88-98.
14. Stratix II DSP Development Board, Reference Manual, Altera Corp., Aug. 2006, http://www.altera.com/literature/manual/mnl-stx2-pro-dsp-dev-kit-ep2s180. pdf.