Hierarchical memory system design for a heterogeneous multi-core processor

Proceedings of the ACM Symposium on Applied Computing

Volumn , Issue , 2008, Pages 1504-1508

  Guo, Jianjun ^a   Lai, Mingche ^a   Pang, Zhengyuan ^a   Huang, Libo ^a   Chen, Fangyuan ^a   Dai, Kui ^a   Wang, Zhiying ^a  

^a NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY   (China)

Author keywords

Heterogeneous; Memory; Multi core

Indexed keywords

ARCHITECTURE; SYSTEMS ANALYSIS;

CORE PROCESSORS; HETEROGENEOUS; HIERARCHICAL MEMORIES; MEMORY; MEMORY BANDWIDTHS; MEMORY SYSTEMS; MULTI-CORE; TRANSPORT TRIGGERED ARCHITECTURES;

COMPUTER ARCHITECTURE;

EID: 56749174001     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1363686.1364039     Document Type: Conference Paper

References (22)

1. H. Peter Hofstee. Power Efficient Processor Architecture and The Cell Processor. Proc. of the 11th International Symposium on High-Performance Computer Architecture (HPCA05) pp. 258-262
2. Overview of UltraSPARC Tl processor. http://www.sun.com/processors/ UltraSPARC-T1/
3. Hammond L., Hubbert B., et al. The Stanford Hydra CMP. IEEE Micro, 2000, 20(2), p71-84.
4. Juan del Cuvillo Weirong Zhu Ziang Hu Guang R. Gao. TiNy Threads: a Thread Virtual Machine for the Cyclops64 Cellular Architecture. Proc. of the IPDPS 2005.
5. Henk Corporaal and Hans Mulder. MOVE: A framework for high-performance processor design. Proc. of Supercomputing91, Albuquerque, November 1991, p692-701.
6. Libo Huang, Li Shen, Kui Dai, Zhiying Wang. A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design. Proc. of the 18th IEEESymposium on Computer Arithmetic (ARITH07), 2007. pp. v-viii.
7. Nuwan S. Jayasena. Memory hierarchy design for stream computing. Stanford University PhD Thesis, 2005.
8. Kenneth M. Wilson and Kunle Olukotun. Designing High Bandwidth On-Chip Caches. Proc. of the 24th ISCA, June 2-4, 1997, Denver, Colorado.
9. M. Horowitz, S. Przybylski, and M. D. Smith. Tutorial on Recent Trends in Processor Design: Reclimbing the Complexity Curve. Western Institute of Computer Science, Stanford University, 1992.
10. Ma Guoqiang, Xu Sushan, Xu Jianjian, Bi Houjie. Design and Optimization of Video Encoder Based on H.264. China Communications. August 2005, p60-66.
11. R. E. Matick and S. E Schuster. Logic-based eDRAM: Origins and rationale for use. IBM J. RES. & DEV. Vol. 49 No. 1 January 2005.
12. T. Juan, T. Lang, and J. J. Navarro. Reducing TLB power requirements. Proc. of the International Symposium on Low Power Electronics and Design, 1997.
13. S. Kim. Low power MMU design for embedded processors. http://supercom.yonsei.ac.kr/temp/sam.ppt
14. I. Kadayif, A. Sivasubramaniam, et al. Generating Physical Addresses Directly for Saving Instruction TLB Energy. Proc. of the 35th International Symposium on Microarchitecture. 2002. p185 -196.
15. J. P. Grossman. A Systolic Array for Implementing LRU Replacement. Project Aries Technical Memo
16. Jianjun Guo, Kui Dai and Zhiying Wang. A Heterogeneous Multi-Core Processor Architecture for High Performance Computing. Proc. of the 11th Asia-Pacific Computer Systems Architecture Conference(ACSAC06), pp.359-365, September 6-8th, 2006. Shanghai, China.
17. Chunho Lee, et al.. MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems. Proc. of the 30th International Symposium on Microarchitecture (MICRO-30 1997). pp.330-335.
18. Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen. Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. Proc. of the 36th International Symposium on Microarchitecture (MICRO-36 2003).
19. Rakesh Kumar, Dean M. Tullsen, et al. Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. Proc. of the 31st Annual International Symposium on Computer Architecture (ISCA'04).
20. Michael Kanellos. Processor, memory may marry in future computers, http://news.zdnet.com/ 2100-9584-22-6120547.html.
21. Tom Krazit. More memory coming to future IBM chips. http://news.com.com/ 2100-1006-3-6159172.html.
22. Leon3 Processor Introduction. http://www.gaisler.com/cms4-5-3/index.php? option=com-c ontent&task=view&.id= 13 &Itemid=53.