-
1
-
-
0000940792
-
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling
-
IEEE Transactions on jun
-
C.-G. Lee, H. Hahn, Y.-M. Seo, S. L. Min, R. Ha, S. Hong, C. Y. Park, M. Lee, and C. S. Kim, "Analysis of cache-related preemption delay in fixed-priority preemptive scheduling," Computers, IEEE Transactions on, vol. 47, no. 6, pp. 700-713, jun 1998.
-
(1998)
Computers
, vol.47
, Issue.6
, pp. 700-713
-
-
Lee, C.-G.1
Hahn, H.2
Seo, Y.-M.3
Min, S.L.4
Ha, R.5
Hong, S.6
Park, C.Y.7
Lee, M.8
Kim, C.S.9
-
2
-
-
1142299880
-
Accurate estimation of cache-related preemption delay
-
ser. CODES+ISSS '03. New York, NY, USA: ACM
-
H. S. Negi, T. Mitra, and A. Roychoudhury, "Accurate estimation of cache-related preemption delay," in Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, ser. CODES+ISSS '03. New York, NY, USA: ACM, 2003, pp. 201-206.
-
(2003)
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
, pp. 201-206
-
-
Negi, H.S.1
Mitra, T.2
Roychoudhury, A.3
-
3
-
-
24944584859
-
Bounding worst-case data cache behavior by analytically deriving cache reference patterns
-
RTAS 2005. 11th IEEE, 7-10
-
H. Ramaprasad and F. Mueller, "Bounding worst-case data cache behavior by analytically deriving cache reference patterns," in Real Time and Embedded Technology and Applications Symposium, 2005. RTAS 2005. 11th IEEE, 7-10 2005, pp. 148 - 157.
-
(2005)
Real Time and Embedded Technology and Applications Symposium, 2005
, pp. 148-157
-
-
Ramaprasad, H.1
Mueller, F.2
-
4
-
-
33749646825
-
Bounding preemption delay within data cache reference patterns for real-time tasks
-
Proceedings of the 12th IEEE, april
-
-, "Bounding preemption delay within data cache reference patterns for real-time tasks," in Real-Time and Embedded Technology and Applications Symposium, 2006. Proceedings of the 12th IEEE, april 2006, pp. 71 - 80.
-
(2006)
Real-time and Embedded Technology and Applications Symposium, 2006
, pp. 71-80
-
-
Ramaprasad, H.1
Mueller, F.2
-
5
-
-
70449581123
-
A new notion of useful cache block to improve the bounds of cache-related preemption delay
-
ECRTS '09. 21st Euromicro Conference on, july
-
S. Altmeyer and C. Burguiere, "A new notion of useful cache block to improve the bounds of cache-related preemption delay," in Real-Time Systems, 2009. ECRTS '09. 21st Euromicro Conference on, july 2009, pp. 109-118.
-
(2009)
Real-time Systems, 2009
, pp. 109-118
-
-
Altmeyer, S.1
Burguiere, C.2
-
6
-
-
0036045884
-
Scratchpad memory: Design alternative for cache on-chip memory in embedded systems
-
New York, NY, USA: ACM
-
R. Banakar, S. Steinke, B.-S. Lee, M. Balakrishnan, and P. Marwedel, "Scratchpad memory: design alternative for cache on-chip memory in embedded systems," in CODES '02: Proceedings of the tenth international symposium on Hardware/software codesign. New York, NY, USA: ACM, 2002, pp. 73-78.
-
(2002)
CODES '02: Proceedings of the Tenth International Symposium on Hardware/Software Codesign
, pp. 73-78
-
-
Banakar, R.1
Steinke, S.2
Lee, B.-S.3
Balakrishnan, M.4
Marwedel, P.5
-
7
-
-
84893786147
-
Assigning program and data objects to scratchpad for energy reduction
-
Proceedings
-
S. Steinke, L. Wehmeyer, B.-S. Lee, and P. Marwedel, "Assigning program and data objects to scratchpad for energy reduction," in Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, 2002, pp. 409-415.
-
(2002)
Design, Automation and Test in Europe Conference and Exhibition, 2002
, pp. 409-415
-
-
Steinke, S.1
Wehmeyer, L.2
Lee, B.-S.3
Marwedel, P.4
-
8
-
-
33646947019
-
Compiler-based approach for exploiting scratch-pad in presence of irregular array access
-
Washington, DC, USA: IEEE Computer Society
-
M. J. Absar and F. Catthoor, "Compiler-based approach for exploiting scratch-pad in presence of irregular array access," in Proceedings of the conference on Design, Automation and Test in Europe - Volume 2, ser. DATE '05. Washington, DC, USA: IEEE Computer Society, 2005, pp. 1162-1167.
-
(2005)
Proceedings of the Conference on Design, Automation and Test in Europe - Volume 2, Ser. DATE '05
, pp. 1162-1167
-
-
Absar, M.J.1
Catthoor, F.2
-
9
-
-
33748607682
-
Analysis of scratch-pad and data-cache performance using statistical methods
-
Asia and South Pacific Conference on
-
J. Absar and F. Catthoor, "Analysis of scratch-pad and data-cache performance using statistical methods," in Design Automation, 2006. Asia and South Pacific Conference on, 2006, pp. 820-825.
-
(2006)
Design Automation, 2006
, pp. 820-825
-
-
Absar, J.1
Catthoor, F.2
-
10
-
-
17044401007
-
Custom design of multi-level dynamic memory management subsystem for embedded systems
-
SIPS 2004. IEEE Workshop on, oct.
-
S. Mamagkakis, D. Atienza, C. Poucet, F. Catthoor, D. Soudris, and J. Mendias, "Custom design of multi-level dynamic memory management subsystem for embedded systems," in Signal Processing Systems, 2004. SIPS 2004. IEEE Workshop on, oct. 2004, pp. 170 - 175.
-
(2004)
Signal Processing Systems, 2004
, pp. 170-175
-
-
Mamagkakis, S.1
Atienza, D.2
Poucet, C.3
Catthoor, F.4
Soudris, D.5
Mendias, J.6
-
11
-
-
84944414413
-
Heterogeneous memory management for embedded systems
-
New York, NY, USA: ACM
-
O. Avissar, R. Barua, and D. Stewart, "Heterogeneous memory management for embedded systems," in CASES '01: Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems. New York, NY, USA: ACM, 2001, pp. 34-43.
-
(2001)
CASES '01: Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
, pp. 34-43
-
-
Avissar, O.1
Barua, R.2
Stewart, D.3
-
12
-
-
84879409036
-
WCET centric data allocation to scratchpad memory
-
RTSS 2005. 26th IEEE International, 8-8 232
-
V. Suhendra, T. Mitra, A. Roychoudhury, and T. Chen, "WCET centric data allocation to scratchpad memory," in Real-Time Systems Symposium, 2005. RTSS 2005. 26th IEEE International, 8-8 2005, pp. 10 pp. -232.
-
(2005)
Real-time Systems Symposium, 2005
, pp. 10
-
-
Suhendra, V.1
Mitra, T.2
Roychoudhury, A.3
Chen, T.4
-
13
-
-
35348912736
-
WCET-directed dynamic scratchpad memory allocation of data
-
ECRTS '07. 19th Euromicro Conference on, 4-6
-
J.-F. Deverge and I. Puaut, "WCET-directed dynamic scratchpad memory allocation of data," in Real-Time Systems, 2007. ECRTS '07. 19th Euromicro Conference on, 4-6 2007, pp. 179-190.
-
(2007)
Real-time Systems, 2007
, pp. 179-190
-
-
Deverge, J.-F.1
Puaut, I.2
-
14
-
-
34548134821
-
Optimal unified data allocation and task scheduling for real-time multi-tasking systems
-
RTAS '07. 13th IEEE, 3-6
-
R. Ghattas, G. Parsons, and A. Dean, "Optimal unified data allocation and task scheduling for real-time multi-tasking systems," in Real Time and Embedded Technology and Applications Symposium, 2007. RTAS '07. 13th IEEE, 3-6 2007, pp. 168-182.
-
(2007)
Real Time and Embedded Technology and Applications Symposium, 2007
, pp. 168-182
-
-
Ghattas, R.1
Parsons, G.2
Dean, A.3
-
15
-
-
77953856974
-
DARTS: Techniques and tools for predictably fast memory using integrated data allocation and real-time task scheduling
-
2010 16th IEEE, 12-15
-
S. Kang and A. G. Dean, "DARTS: Techniques and tools for predictably fast memory using integrated data allocation and real-time task scheduling," in Real-Time and Embedded Technology and Applications Symposium (RTAS), 2010 16th IEEE, 12-15 2010, pp. 333-342.
-
(2010)
Real-time and Embedded Technology and Applications Symposium (RTAS)
, pp. 333-342
-
-
Kang, S.1
Dean, A.G.2
-
16
-
-
0024933416
-
SMART (strategic memory allocation for realtime) cache design
-
Proceedings, 5-7
-
D. Kirk, "SMART (strategic memory allocation for realtime) cache design," in Real Time Systems Symposium, 1989., Proceedings., 5-7 1989, pp. 229-237.
-
(1989)
Real Time Systems Symposium, 1989
, pp. 229-237
-
-
Kirk, D.1
-
17
-
-
84880896550
-
SMART (strategic memory allocation for real-time) cache design using the mips r3000
-
Proceedings., 11th, Dec
-
D. Kirk and J. Strosnider, "SMART (strategic memory allocation for real-time) cache design using the mips r3000," in Real-Time Systems Symposium, 1990. Proceedings., 11th, Dec 1990, pp. 322-330.
-
(1990)
Real-time Systems Symposium, 1990
, pp. 322-330
-
-
Kirk, D.1
Strosnider, J.2
-
18
-
-
84976714711
-
Compiler support for software-based cache partitioning
-
November
-
F. Mueller, "Compiler support for software-based cache partitioning," SIGPLAN Not., vol. 30, pp. 125-133, November 1995.
-
(1995)
SIGPLAN Not.
, vol.30
, pp. 125-133
-
-
Mueller, F.1
-
19
-
-
0036991624
-
Low-complexity algorithms for static cache locking in multitasking hard real-time systems
-
RTSS 2002. 23rd IEEE
-
I. Puaut and D. Decotigny, "Low-complexity algorithms for static cache locking in multitasking hard real-time systems," in Real-Time Systems Symposium, 2002. RTSS 2002. 23rd IEEE, 2002, pp. 114 - 123.
-
(2002)
Real-time Systems Symposium, 2002
, pp. 114-123
-
-
Puaut, I.1
Decotigny, D.2
-
20
-
-
70349923099
-
Scratchpad memories vs locked caches in hard real-time systems: A quantitative comparison
-
DATE '07, 16-20
-
I. Puaut and C. Pais, "Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison," in Design, Automation Test in Europe Conference Exhibition, 2007. DATE '07, 16-20 2007, pp. 1-6.
-
(2007)
Design, Automation Test in Europe Conference Exhibition, 2007
, pp. 1-6
-
-
Puaut, I.1
Pais, C.2
-
21
-
-
0030675463
-
Cache miss equations: An analytical representation of cache misses
-
New York, NY, USA: ACM
-
S. Ghosh, M. Martonosi, and S. Malik, "Cache miss equations: an analytical representation of cache misses," in ICS '97: Proceedings of the 11th international conference on Supercomputing. New York, NY, USA: ACM, 1997, pp. 317-324.
-
(1997)
ICS '97: Proceedings of the 11th International Conference on Supercomputing
, pp. 317-324
-
-
Ghosh, S.1
Martonosi, M.2
Malik, S.3
-
22
-
-
3042658412
-
Cache-aware scratchpad allocation algorithm
-
Proceedings 16-20 Vol.2
-
M. Verma, L. Wehmeyer, and P. Marwedel, "Cache-aware scratchpad allocation algorithm," in Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, vol. 2, 16-20 2004, pp. 1264 - 1269 Vol.2.
-
(2004)
Design, Automation and Test in Europe Conference and Exhibition, 2004
, vol.2
, pp. 1264-1269
-
-
Verma, M.1
Wehmeyer, L.2
Marwedel, P.3
-
23
-
-
0030686025
-
Efficient utilization of scratch-pad memory in embedded processor applications
-
ED TC 97. Proceedings, 17-20
-
P. Panda, N. Dutt, and A. Nicolau, "Efficient utilization of scratch-pad memory in embedded processor applications," in European Design and Test Conference, 1997. ED TC 97. Proceedings, 17-20 1997, pp. 7-11.
-
(1997)
European Design and Test Conference, 1997
, pp. 7-11
-
-
Panda, P.1
Dutt, N.2
Nicolau, A.3
-
24
-
-
23044524059
-
On-chip vs. off-chip memory: The data partitioning problem in embedded processor-based systems
-
P. R. Panda, N. D. Dutt, and A. Nicolau, "On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems," ACM Transactions on Design Automation and Electronic Systems, vol. 5, no. 3, pp. 682-704, 2000.
-
(2000)
ACM Transactions on Design Automation and Electronic Systems
, vol.5
, Issue.3
, pp. 682-704
-
-
Panda, P.R.1
Dutt, N.D.2
Nicolau, A.3
-
25
-
-
84962779213
-
Mibench: A free, commercially representative embedded benchmark suite
-
WWC-4. 2001 IEEE International Workshop on, dec.
-
M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, and R. Brown, "Mibench: A free, commercially representative embedded benchmark suite," in Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop on, dec. 2001, pp. 3 - 14.
-
(2001)
Workload Characterization, 2001
, pp. 3-14
-
-
Guthaus, M.1
Ringenberg, J.2
Ernst, D.3
Austin, T.4
Mudge, T.5
Brown, R.6
-
26
-
-
84862010662
-
-
The FreeRTOS Project, http://www.freertos.org.
-
-
-
|