Design and fabrication of a perpendicular magnetic tunnel junction based nonvolatile programmable switch achieving 40% less area using shared-control transistor structure

Journal of Applied Physics

Volumn 115, Issue 17, 2014, Pages

  Suzuki, D ^a   Natsui, M ^a   Mochizuki, A ^a   Miura, S ^b   Honjo, H ^b   Kinoshita, K ^a   Fukami, S ^a   Sato, H ^a   Ikeda, S ^a   Endoh, T ^a   Ohno, H ^a   Hanyu, T ^a  

^a TOHOKU UNIVERSITY   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FABRICATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EFFECTIVE AREA; MAGNETIC TUNNEL JUNCTION; NON-VOLATILE; NON-VOLATILE MEMORY; PROGRAMMABLE SWITCHES; ROUTING INFORMATION; TEST CHIPS; TRANSISTOR STRUCTURE;

MAGNETIC DEVICES;

EID: 84903892358     PISSN: 00218979     EISSN: 10897550     Source Type: Journal    
DOI: 10.1063/1.4868332     Document Type: Conference Paper

References (18)

1. I. Kuon and J. Rose, IEEE Trans. VLSI Syst. 19, 71 (2011). 10.1109/TVLSI.2009.2031318
2. E. Pop, Nano Res. 3, 147 (2010). 10.1007/s12274-010-1019-z
3. J. Greene, S. Kaptanoglu, W. Feng, V. Hecht, J. Landry, F. Li, A. Krouglyanskiy, M. Morosan, and V. Pevzner, in Proc. ACM Int. Symp. FPGA (2011), p. 87.
4. Y. Y. Liauw, Z. Zhang, W. Kim, A. E. Gamal, and S. S. Wong, IEEE Int. Conf. Solid-State Circuits Dig. Tech. Pap. 2012, 406.
5. M. Iida, M. Koga, K. Inoue, M. Amagasaki, Y. Ichida, M. Saji, J. Iida, and T. Sueyoshi, IEICE Trans. Electron. E94-C, 548 (2011). 10.1587/transele.E94. C.548
6. M. Miyamura, M. Tada, T. Sakamoto, N. Banno, K. Okamoto, N. Iguchi, and H. Hada, Int. Electron Devices Meet., Tech. Dig. 2012, 247. 10.1109/IEDM.2012. 6479020
7. W. Zhao, E. Belhaire, V. Javerliac, C. Chappert, and B. Dieny, in Proc. Int. Conf. Inter. Circuit Design and Technologies (2006), p. 1.
8. W. Zhao, E. Belhaire, C. Chappert, F. Jacquet, and P. Mazoyer, Phys. Status Solidi A 205, 1373 (2008). 10.1002/pssa.200778135
9. D. Suzuki, M. Natsui, S. Ikeda, H. Hasegawa, K. Miura, J. Hayakawa, T. Endoh, H. Ohno, and T. Hanyu, Symp. VLSI Circuits Dig. Tech. Pap. 2009, 80.
10. S. Yamamoto, Y. Shuto, and S. Sugahara, Jpn. J. Appl. Phys., Part I 51, 11PB02 (2012). 10.7567/JJAP.51.11PB02
11. D. Suzuki, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, J. Appl. Phys. 111, 07E318 (2012). 10.1063/1.3672411
12. D. Suzuki, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, Jpn. J. Appl. Phys., Part I 51, 04DM02 (2012). 10.7567/JJAP.51.04DM02
13. S. Ikeda, K. Miura, H. Yamamoto, K. Mizunuma, H. D. Gan, M. Endo, S. Kanai, J. Hayakawa, F. Matsukura, and H. Ohno, Nature Mater. 9, 721 (2010). 10.1038/nmat2804
14. C. Yoshida, T. Ochiai, Y. Iba, Y. Yamazaki, K. Tsunoda, A. Takahashi, and T. Sugii, Symp. VLSI Technol. Dig. Tech. Pap. 2012, 59. 10.1109/VLSIT.2012. 6242460
15. Y. Shuto, S. Yamamoto, and S. Sugahara, J. Appl. Phys. 105, 07C933 (2009). 10.1063/1.3076895
16. N. Sakimura, R. Nebashi, Y. Tsuji, H. Honjo, H. Koike, T. Ohsawa, S. Fukami, T. Hanyu, H. Ohno, and T. Endoh, in Proc. IEEE Int. Conf. Circuits and Systems (2012), p. 1971.
17. T. Min, J. Z. Sun, R. Beach, D. Tang, and P. Wang, J. Appl. Phys. 105, 07D126 (2009). 10.1063/1.3063672
18. S.-C. Oh, S.-Y. Park, A. Manchon, M. Chshiev, J.-H. Han, H.-W. Lee, J.-E. Lee, K.-T. Nam, Y. Jo, Y.-C. Kong, B. Dieny, and K.-J. Lee, Nat. Phys. 5, 898 (2009). 10.1038/nphys1427