Demonstration of non-volatile working memory through interface engineering in STT-MRAM

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2012, Pages 59-60

  Yoshida, C ^a   Ochiai, T ^a   Iba, Y ^a   Yamazaki, Y ^a   Tsunoda, K ^a   Takahashi, A ^a   Sugii, T ^a  

^a Low power Electronics Association and Project LEAP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTERFACE ENGINEERING; LOW RESISTANCE; MAGNETIC TUNNEL JUNCTION; MAGNETORESISTANCE RANDOM ACCESS MEMORY; MAGNETORESISTANCE RATIO; MGO BARRIER; NON-VOLATILE; OPERATION VOLTAGE; POST-OXIDATION; SEED LAYER; SPIN TRANSFER TORQUE; SWITCHING VOLTAGES; WORKING MEMORIES;

ELECTRONIC PROPERTIES; MAGNESIUM; MAGNETIC DEVICES; MAGNETORESISTANCE;

MRAM DEVICES;

EID: 84866526141     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2012.6242460     Document Type: Conference Paper

References (4)

1. M. Hosomi et al., IEDM Tech. Dig., p. 459, (2005).
2. YS. Choi et al., Jpn. J Appl. Phys. 48, (2009) 120214.
3. C. Yoshida et al., Dig. of MMM 2011, AF-13, Oct, 2011.
4. S. Amara-Dababi et al., Appl. Phys. Lett. 99 (2011) 083501.