Six-input lookup table circuit with 62 fewer transistors using nonvolatile logic-in-memory architecture with series/parallel-connected magnetic tunnel junctions

Journal of Applied Physics

Volumn 111, Issue 7, 2012, Pages

  Suzuki, D ^a   Natsui, M ^a   Endoh, T ^a   Ohno, H ^a   Hanyu, T ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP AREAS; LOGIC-IN-MEMORY ARCHITECTURE; LOOK UP TABLE; LOOKUPS; MAGNETIC TUNNEL JUNCTION; NON-VOLATILE; PROCESS VARIATION; PROGRAMMABILITY; RESISTANCE VALUES; RESISTANCE VARIATIONS; SENSING MARGIN; STATIC RANDOM ACCESS MEMORY; TABLE CIRCUITS; TRANSISTOR COUNT;

MAGNETIC DEVICES; MEMORY ARCHITECTURE; VLSI CIRCUITS;

LOGIC CIRCUITS;

EID: 84861723047     PISSN: 00218979     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.3672411     Document Type: Conference Paper

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