Nonvolatile power-gating field-programmable gate array using nonvolatile static random access memory and nonvolatile flip-flops based on pseudo-spin-transistor architecture with spin-transfer-torque magnetic tunnel junctions

Japanese Journal of Applied Physics

Volumn 51, Issue 11 PART2, 2012, Pages

  Yamamoto, Shuu'ichirou ^a,b   Shuto, Yusuke ^a,b   Sugahara, Satoshi ^a,b  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT CONFIGURATIONS; EFFICIENT POWER; FINE GRANULARITY; JAPAN SOCIETY OF APPLIED PHYSICS; LOGIC BLOCKS; MAGNETIC TUNNEL JUNCTION; MICRO ARCHITECTURES; NON-VOLATILE; NON-VOLATILE MEMORIES; POWER-GATING; REDUCTION TECHNIQUES; STATIC RANDOM ACCESS MEMORY;

COMPUTER ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FLIP FLOP CIRCUITS; STATIC RANDOM ACCESS STORAGE;

MAGNETIC DEVICES;

EID: 84871395183     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.51.11PB02     Document Type: Conference Paper

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