Exploring area and delay tradeoffs in FPGAs with architecture and automated transistor design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 1, 2011, Pages 71-84

  Kuon, Ian ^a,b   Rose, Jonathan ^a  

^a UNIVERSITY OF TORONTO   (Canada)

^b Altera Toronto Technology Center   (Canada)

Author keywords

Architecture; area delay tradeoffs; field programmable gate array (FPGAs); transistor sizing

Indexed keywords

AREA DELAY TRADEOFFS; CIRCUIT DESIGNS; FPGA VENDORS; LUT SIZE; POWER CONSUMPTION; POWER DESIGN; TRANSISTOR DESIGNS; TRANSISTOR SIZE; TRANSISTOR SIZING;

ARCHITECTURAL DESIGN; COMMERCE; INTEGRATED CIRCUIT MANUFACTURE; LOGIC GATES; TRANSISTORS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 78650921963     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2031318     Document Type: Article

References (46)

1. Stratix IV Device Handbook Volumes 1-4 SIV5V1-1.0, Altera Corporation, May 2008 [Online]. Available: http://www.altera.com/literature/ hb/stratix-iv/stratix4-handbook.pdf
2. Lattice SC/M Family Handbook, Version 02.1, DS 1004, Lattice Semiconductor Corporation, Jun. 2008 [Online]. Available: http://www. latticesemi. com/dynamic/viewdocument.cfm?document-id=19028
3. Virtex-5 User Guide uG190 (v4.0), Xilinx, Mar. 2008 [Online]. Available: http://www.xilinx.com/support/documentation/ user-guides/ug190.pdf
4. Cyclone III Device Handbook CIII5V1-1.2, Altera Corporation, Sep. 2007 [Online]. Available: http://www.altera.com/literature/ hb/cyc3/cyclone3- handbook.pdf
5. Lattice ECP2/M Family Handbook, Version 02.9, HB 1003, Lattice Semiconductor Corporation, Jul. 2007 [Online]. Available: http://www. latticesemi.com/dynamic/viewdocument.cfm?document- id=21733
6. Spartan-3E, ver. 3.4, Xilinx, Nov. 2006 [Online]. Available: http://direct. xilinx.com/bvdocs/publications/ds312.pdf
7. I. Kuon and J. Rose, "Measuring the gap between FPGAs and ASICs," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 26, no. 2, pp. 203-215, Feb. 2007.
8. G. Lemieux, E. Lee, M. Tom, and A. Yu, "Directional and singledriver wires in FPGA interconnect," in Proc. IEEE Int. Conf. Field-Programmable Technol., Dec. 2004, pp. 41-48.
9. E. Ahmed and J. Rose, "The effect of LUT and cluster size on deepsubmicron FPGA performance and density," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 3, pp. 288-298, Mar. 2004.
10. F. Li, Y. Lin, L. He, D. Chen, and J. Cong, "Power modeling and characteristics of field programmable gate arrays," IEEE Trans. Comput.- Aided Des. Integr. Circuits Syst., vol. 24, no. 11, pp. 1712-1724, Nov. 2005.
11. V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep- Submicron FPGAs. Norwell, MA: Kluwer, 1999.
12. L. Cheng et al., "Device and architecture cooptimization for FPGA power reduction," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 26, no. 7, pp. 1211-1221, Jul. 2007.
13. J. M. Rabaey, Digital Integrated Circuits a Design Perspective. Englewood Cliffs, NJ: Prentice Hall, 1996.
14. A. R. Conn, I. M. Elfadel, J. W. W. Molzen, P. R. O'Brien, P. N. Strenski, C. Visweswariah, and C. B. Whan, "Gradient-based optimization of custom circuits using a static-timing formulation," in Proc. DAC, New York, 1999, pp. 452-459.
15. C.-P. Chen et al., "Fast and exact simultaneous gate and wire sizing by langrangian relaxation," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 18, no. 7, pp. 1014-1025, Jul. 1999.
16. J. P. Fishburn and A. Dunlop, "TILOS: A posynomial programming approach to transistor sizing," in Proc. Int. Conf. Comput.-Aided Des., Nov. 1985, pp. 326-328.
17. S. S. Sapatnekar et al., "An exact solution to the transistor sizing problem for CMOS circuits using convex optimization," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 12, no. 11, pp. 1621-1634, Nov. 1993.
18. K. Compton et al., "Flexible routing architecture generation for domain-specific reconfigurable subsystems," in Proc. Int. Conf. Field Programmable Logic Appl., 2002, pp. 59-68.
19. I. Kuon and J. Rose, "Area and delay tradeoffs in the circuit and architecture design of FPGAs," in Proc. ISFPGA, New York, 2008, pp. 149-158.
20. I. Kuon and J. Rose, "Automated transistor sizing for FPGA architecture exploration," in Proc. DAC, New York, 2008, pp. 792-795.
21. S. D. Brown, R. Francis, J. Rose, and Z. Vranesic, Field-Programmable Gate Arrays. Norwell, MA: Kluwer, 1992.
22. S. P. Young, T. J. Bauer, K. Chaudhary, and S. Krishnamurthy, "FPGA Repeatable Interconnect Structure With Bidirectional and Unidirectional Interconnect Lines," U.S. 5 942 913, Aug. 24, 1999.
23. D. Lewis et al., "The Stratix™ routing and logic architecture," Proc. ISFPGA, pp. 12-20, 2003.
24. Stratix III Device Handbook, sIII5V1-1.4 Altera Corporation, Nov. 2007 [Online]. Available: http://www.altera.com/literature/ hb/stx3/stratix3- handbook.pdf
25. D. Tavana et al., "FPGA ArchitectureWith Repeatable Tiles Including Routing Matrices and Logic Matrices," U.S. 5,682,107, Oct. 28, 1997.
26. P. Chow et al., "The design of a SRAM-based field programmable gate array-part II: Circuit design and layout," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 7, no. 3, pp. 321-330, Sep. 1999.
27. D. Lewis et al., "The Stratix II logic and routing architecture," in Proc. ISFPGA., New York, 2005, pp. 14-20.
28. E. Lee et al., "Interconnect driver design for long wires in field-programmable gate arrays," Proc. FPT, pp. 89-96, Dec. 2006.
29. I. Kuon, "Measuring and navigating the gap between FPGAs and ASICs," Ph.D. dissertation, Univ. Toronto, ON, Canada, 2008.
30. STMicroelectronics, 90 nm CMOS090 Design Platform. 2005 [Online]. Available: http://www.st.com/stonline/products/technologies/ soc/90plat.htm
31. J. Luu et al., "VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling," in Proc. ISFPGA, New York, 2009, pp. 133-142.
32. V. Betz and J. Rose, "Circuit design, transistor sizing and wire layout of FPGA interconnect," Proc. CICC, pp. 171-174, 1999.
33. M. Hutton et al., "Interconnect enhancements for a high-speed PLD architecture," in Proc. ISFPG, New York, 2002, pp. 3-10.
34. J. H. Anderson and F. N. Najm, "Low-power programmable routing circuitry for FPGAs," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., Washington, DC, 2004, pp. 602-609.
35. S. P. Young, "Six-Input Multiplexer With Two Gate Levels and Three Memory Cells," U.S. 5 744 995, Apr. 17, 1998.
36. J. K. Ousterhout, "Switch-level delay models for digital MOS VLSI," in Proc. DAC, 1984, pp. 542-548.
37. J. Rubinstein, P. Penfield, and M. A. Horowitz, "Signal delay in RC tree networks," IEEE Trans. Comput.-Aided Des. of Integr. Circuits Syst., vol. 2, no. 3, pp. 202-211, Jul. 1983.
38. I. Sutherland, R. Sproule, and D. Harris, Logical Effort : Designing Fast CMOS circuits. San Diego, CA: Morgan Kaufmann, 1999.
39. S. Yang, Logic Synthesis and Optimization Benchmarks User Guide Version 3.0, Microelectronics Center of North Carolina, 1991.
40. J. Cong, J. Peck, and Y. Ding, "RASP:Ageneral logic synthesis system for SRAM-based FPGAs," in Proc. ISFPGA, New York, 1996, pp. 137-143.
41. A. Marquardt, V. Betz, and J. Rose, "Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density," Proc. FPGA, pp. 37-46, 1999.
42. V. Betz and J. Rose, "VPR: A new packing, placement and routing tool for FPGA research," in Proc. 7th Int. Workshop Field-Programmable Logic, 1997, pp. 213-222.
43. J. E. Weber, Mathematical Analysis: Business and Economic Applications, 3rd ed. New York: Harper & Row, 1976.
44. E. Ahmed, "The effect of logic block granularity on deep-submicron FPGA performance and density," Master's thesis, Univ. Toronto, ON, Canada, 2001.
45. Stratix II Device Handbook SII5V1-4.3, Altera Corporation, May 2007 [Online]. Available: http://www.altera.com/literature/ hb/stx2/stratix2- handbook.pdf
46. Cyclone II Device Handbook CII5V1-3.3, Altera Corporation, Feb. 2008 [Online]. Available: http://www.altera.com/literature/ hb/cyc2/cyc2-cii5v1.pdf