Toward a scalable working set size estimation method and its application for chip multiprocessors

IEEE Transactions on Computers

Volumn 63, Issue 6, 2014, Pages 1567-1579

  Dani, Aparna Mandke ^a   Amrutur, Bharadwaj ^a   Srikant, Y N ^a  

^a INDIAN INSTITUTE OF SCIENCE   (India)

Author keywords

Chip multiprocessors (CMPs); variable cache associativity; working set size (WSS) estimation

Indexed keywords

MULTIPROCESSING SYSTEMS;

ASSOCIATIVITY; CHIP MULTI-PROCESSORS (CMPS); CHIP MULTIPROCESSOR; CHIP MULTIPROCESSORS; ENERGY DELAY PRODUCT; MEMORY ACCESS LATENCY; NON-UNIFORM CACHE ARCHITECTURE; WORKING SET;

MEMORY ARCHITECTURE;

EID: 84903172278     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2012.291     Document Type: Article

References (41)

1. AMD Opteron Processors. (2014). [Online]. Available: http://www. amd.com/enus/products/server/6000/6200#
2. Intel Nehalem. (2014). [Online]. Available: http://www.3dnow. net/phpBB2/viewtopic.php?f=1&t=1474&p=6720
3. D. Weiss, J. J. Wuu, and V. Chin, "The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor," in Proc. Int. Solid-State Circuits Conf. (ISSCC'02), 2002, pp. 1523-1529. (Pubitemid 35432174)
4. A. S. Dhodapkar and J. E. Smith, "Managing multi-configuration hardware via dynamic working set analysis," in Proc. Int. Symp. Comput. Archit. (ISCA'02), 2002, pp. 233-244. (Pubitemid 34691865)
5. D. H. Albonesi, "Selective cache ways: On-demand cache resource allocation," in Proc. 32nd Annu. IEEE/ACM Int. Symp. Microarchit. (MICRO'99), 1999, pp. 248-259.
6. A. V. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, and X. Ji, "Adapting cache line size to application behavior," in Proc. Int. Conf. Supercomput. (ICS'99), 1999, pp. 145-154.
7. S. Kaxiras, Z. Hu, and M. Martonosi, "Cache decay: Exploiting generational behavior to reduce cache leakage power," in Proc. Int. Symp. Comput. Archit. (ISCA'01), 2001, pp. 240-251. (Pubitemid 32825409)
8. R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas, "Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures," in Proc. 32nd Annu. IEEE/ACM Int. Symp. Microarchit. (MICRO'00), 2000, pp. 245-257. (Pubitemid 32255847)
9. M. Hammoud, S. Cho, and R. Melhem, "Dynamic cache clustering for chip multiprocessors," in Proc. Int. Conf. Supercomput. (ICS'09), 2009, pp. 56-67.
10. C. Kim, D. Burger, and S. W. Keckler, "An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches," in Proc. 10th Int. Conf. Archit. Support Program. Lang. Oper. Syst. (ASPLOS'02), 2002, pp. 211-222. (Pubitemid 44892235)
11. A. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, and C. A. Prete, "Way adaptable DNUCA caches," Int. J. High Perform. Syst. Archit., pp. 215-228, Aug. 2010.
12. S.-H. Yang, B. Falsafi, M. D. Powell, and T. N. Vijaykumar, "Exploiting choice in resizable cache design to optimize deepsubmicron processor energy-delay," in Proc. 8th Int. Symp. High-Perform. Comput. Archit. (HPCA'02), 2002, pp. 151-161.
13. A. S. Dhodapkar and J. E. Smith, "Comparing program phase detection techniques," in Annu. Int. Symp. Microarchit. (MICRO'03), 2003, pp. 217-227.
14. M. Van Biesbrouck, T. Sherwood, and B. Calder, "Aco-phase matrix to guide simultaneous multithreading simulation," in Proc. IEEE Int. Symp. Perform. Anal. Syst. Softw. (ISPASS'04), 2004, pp. 45-56.
15. J. Renau, B. Fraguela, J. Tuck, W. Liu, M. Prvulovic, L. Ceze, S. Sarangi, P. Sack, K. Strauss, and P. Montesinos. (2005). SESC Simulator [Online]. Available: http://sesc.sourceforge.net
16. M. M. K. Martin, D. J. Sorin, B. M. Beckmann, M. R. Marty, M. Xu, A. R. Alameldeen, K. E. Moore, M. D. Hill, and D. A. Wood, "Multifacet general execution-driven multiprocessor simulator (gems) toolset," SIGARCH Comput. Archit. News, pp. 92-99, 2005.
17. D. Wang, B. Ganesh, N. Tuaycharoen, K. Baynes, A. Jaleel, and B. Jacob, "DRAMsim: A memory system simulator," SIGARCH Comput. Archit. News, pp. 100-107, 2005.
18. Micron DRAM Power Data Sheet. (2012). [Online]. Available: http://www.micron.com/products/partdetail?part=MT47H128M8HQ-3E
19. R. Nagpal, A. Madan, A. Bhardwaj, and Y. N. Srikant, "Intacte: An interconnect area, delay, and energy estimation tool for microarchitectural explorations," in Proc. Int. Conf. Compilers, Archit., Synth. Embedded Syst. (CASES'07), 2007, pp. 238-247. (Pubitemid 351204007)
20. N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi. (2009). CACTI 6.0: A Tool to Model Large Caches [Online]. Available: http://www.hpl.hp.com/ techreports/2009/HPL-2009-85.html
21. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, "The SPLASH-2 programs: Characterization and methodological considerations," in Proc. 22nd Annu. Int. Symp. Comput. Archit. (ISCA'95), 1995, pp. 24-36.
22. M. lap Li, R. Sasanka, S. V. Adve, Y. kuang Chen, and E. Debes, "The ALPBench benchmark suite for complex multimedia applications," in 9th IEEE Int. Symp. Wearable Comput. (ISWC'05), 2005, pp. 34-45. (Pubitemid 44460133)
23. C. Bienia, S. Kumar, J. P. Singh, and K. Li, "The PARSEC benchmark suite: Characterization and architectural implications," in Proc. Parallel Archit. Compil. Tech. (PACT'08), 2008, pp. 72-81.
24. R. Manikantan and R. Govindrajan, "Performance oriented prefetching enhancements using commit stalls," J. Instruct.-Level Parallelism, 2011.
25. SPEC Benchmarks. [Online]. Available: http://www.spec.org/
26. Xeon Processor. (2014). [Online]. Available: http://ark.intel.com/ products/codename/22796/Woodcrest
27. E. Dubrova and S. S. Mansouri, "A BDD-based approach to constructing LFSRs for parallel CRC encoding," in Proc. IEEE 42nd Int. Symp. Multiple-Valued Logic, 2012, pp. 128-133.
28. A. Janapsatya, A. Ignjatović, and S. Parameswaran, "Finding optimal L1 cache configuration for embedded systems," in Proc. 11th Asia and South Pacific Des. Autom. Conf. (ASPDAC'06), 2006, pp. 796-801. (Pubitemid 44376028)
29. M. Powell, S. hyun Yang, B. Falsafi, K. Roy, S. Member, and T. N. Vijaykumar, "Reducing leakage in a high-performance deepsubmicron instruction cache," IEEE Trans. Very Large Scale Integr. Syst., 2001.
30. A. Jaume, G. Antonio, V. Xavier, and B. Micheal, "IATAC: A smart predictor to turn-off L2 cache lines," in ACM Trans. Archit. Code Optimiz., 2005.
31. H. Zhou, M. C. Toburen, E. Rotenberg, and T. M. Conte, "Adaptive mode control: A static-power-efficient cache design," in Proc. Int. Conf. Parallel Archit. Compil. Tech. (PACT'01), 2001, pp. 61-70. (Pubitemid 33085425)
32. R. Koller, A. Verma, and R. Rangaswami, "Estimating application cache requirement for provisioning caches in virtualized systems," in MASCOTS, 2011, pp. 55-62.
33. S.Dropsho,A.Buyuktosunoglu,R.Balasubramonian,D.H.Albonesi, S.Dwarkadas, G. Semeraro, G.Magklis, and M. L. Scott, "Integrating adaptive on-chip storage structures for reduced dynamic power," in Proc. Int. Conf. Parallel Archit. Compil. Tech. (PACT'02), 2002, pp. 141-152.
34. A. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, and C. A. Prete, "A power-efficient migration mechanism for D-NUCA caches." in Proc. Des. Autom. Test Eur. (DATE'09), 2009, pp. 598-601.
35. K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. Mudge, "Drowsy caches: Simple techniques for reducing leakage power," in Proc. Int. Symp. Comput. Archit. (ISCA'02), 2002, pp. 148-157. (Pubitemid 34691858)
36. M. Powell, S. hyun Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar, "Gated-VDD: A circuit technique to reduce leakage in cache memories," in Proc. Int. Symp. Low Power Electron. Des. (ISLPED'00), 2000, pp. 90-95.
37. G. Gammie, A. Wang, H. Mair, R. Lagerquist, R. Philippe, G. Sumanth, and K. Uming, "Smartreflex power and performance management technologies for 90 nm, 65 nm, and 45 nm mobile application processors," Proc. IEEE, 2010.
38. B. Calhoun and A. Chandrakasan, "Static noise margin variation for sub-thresholdSRAM65-nm CMOS," in IEEE J. on Solid State Circuits, 2006.
39. V. Chandra and R. Aitken, "Impact of voltage scaling on nanoscale SRAM reliability," in Proc. Des. Autom. Test Eur. (DATE'09), 2009, pp. 387-392.
40. V. Chandra and R. Aitken, "Impact of technology and voltage scaling on the soft error susceptibility in nanoscale CMOS," in Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Syst., 2008, pp. 114-122.
41. S. H. Shin, S. W. Chung, E.-Y. Chung, and C. S. Jhon, "Adopting the drowsy technique for instruction caches:Asoft error perspective," in Proc. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., pp. 1772-1779, 2008.