Impact of technology and voltage scaling on the soft error susceptibility in nanoscale CMOS

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2008, Pages 114-122

  Chandra, Vikas ^a   Aitken, Robert ^a  

^a ARM R and D ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

45NM TECHNOLOGY; 65NM TECHNOLOGY; BIT CELL; NANOSCALE CMOS; NOMINAL VOLTAGE; SAVE ENERGY; SILICON CHIP; SIMULATION METHODOLOGY; SOFT ERROR; SUPPLY VOLTAGES; TECHNOLOGY NODES; TECHNOLOGY SCALING; VOLTAGE-SCALING;

ERROR CORRECTION; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; PROBABILITY; PROBABILITY DENSITY FUNCTION; TECHNOLOGY;

QUALITY ASSURANCE;

EID: 67649976852     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFT.2008.50     Document Type: Conference Paper

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