The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 11, 2002, Pages 1523-1529

  Weiss, Don ^a   Wuu, John J ^a   Chin, Victor ^b  

^a HEWLETT PACKARD COMPANY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Cache memories; Memory; Memory architectures; Microprocessors; Random access memories

Indexed keywords

ALUMINUM; BANDWIDTH; DECODING; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE; RELIABILITY;

ARRAY EFFICIENCY; ON CHIP LEVEL THREE CACHE; SUBARRAYS;

CACHE MEMORY;

EID: 0036858572     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.802354     Document Type: Article

References (6)

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