7-nm FinFET CMOS design enabled by stress engineering using Si, Ge, and Sn

IEEE Transactions on Electron Devices

Volumn 61, Issue 5, 2014, Pages 1222-1230

  Gupta, Suyog ^a   Moroz, Victor ^b   Lee, Smith ^b   Lu, Qiang ^b   Saraswat, Krishna C ^a  

^a Stanford University   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

FinFET; germanium; germanium tin; stress engineering

Indexed keywords

DESIGN; GERMANIUM; SILICON; TIN;

FINFET; GERMANIUM-TIN; PERFORMANCE BENEFITS; SIMULATION STUDIES; STRAIN-RELAXED BUFFER LAYERS; STRESS ENGINEERING; TECHNOLOGY NODES; TECHNOLOGY SCALING;

INTEGRATED CIRCUITS;

EID: 84899936293     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2014.2311129     Document Type: Article

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