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Volumn , Issue , 1999, Pages 152-157

Design of an automatic testing for FPGAS

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT DESIGN; STATIC RANDOM ACCESS STORAGE;

EID: 84895122640     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETW.1999.804522     Document Type: Conference Paper
Times cited : (11)

References (13)
  • 2
    • 0032099764 scopus 로고    scopus 로고
    • Testing con-figurable lut-based FPGA'S
    • June
    • W. K. Huang, F. J. Meyer and F. Lombardi, "Testing Con-figurable LUT-Based FPGA's, " IEEE trans. on VLSI, Vol. 6, No. 2, pp. 276-283, June 1998.
    • (1998) IEEE Trans. on VLSI , vol.6 , Issue.2 , pp. 276-283
    • Huang, W.K.1    Meyer, F.J.2    Lombardi, F.3
  • 3
    • 0029700925 scopus 로고    scopus 로고
    • A general technique for testing FPGAS
    • priceton NJ
    • W. K. Huang and F. Lombardi, "A general technique for testing FPGAs, " IEEE VLSI test symposium, priceton NJ, pp. 450-455, 1996.
    • (1996) IEEE VLSI Test Symposium , pp. 450-455
    • Huang, W.K.1    Lombardi, F.2
  • 5
    • 0031337017 scopus 로고    scopus 로고
    • A XOR-Tree based technique for constant testability of configurable FPGAS
    • W. K. Huang, F. J. Meyer and F. Lombardi, "A XOR-Tree based technique for constant testability of configurable FPGAs, " Asian Test Symposium, pp. 248-253, 1997.
    • (1997) Asian Test Symposium , pp. 248-253
    • Huang, W.K.1    Meyer, F.J.2    Lombardi, F.3
  • 7
    • 0030652669 scopus 로고    scopus 로고
    • Test of RAM- Based FPGA: Methodology and Application to the inter- connect structure
    • IEEE CS Press
    • M. Renovell, J. Figueras, and Y. Zorian, "Test of RAM- Based FPGA: Methodology and Application to the inter- connect structure, " Proc. 15th IEEE VLSI Test symp., IEEE CS Press, pp. 204-209, 1997.
    • (1997) Proc. 15th IEEE VLSI Test Symp , pp. 204-209
    • Renovell, M.1    Figueras, J.2    Zorian, Y.3
  • 11
    • 0032320309 scopus 로고    scopus 로고
    • Detection of bridging faults in logic resources of con-gurable FPGA using IDDQ
    • L. Zhao, D. M. walker and F. Lombardi, "Detection Of Bridging Faults In Logic Resources of Con-gurable FPGA Using IDDQ, " International Test Conference, pp. 1037-1046, 1998.
    • (1998) International Test Conference , pp. 1037-1046
    • Zhao, L.1    Walker, D.M.2    Lombardi, F.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.