XOR-tree based technique for constant testability of configurable FPGAs

Proceedings of the Asian Test Symposium

Volumn , Issue , 1997, Pages 248-253

  Huang, W K ^a   Zhang, M Y ^a   Meyer, F J ^a   Lombardi, F ^a  

^a FUDAN UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

LOGIC GATES; MATHEMATICAL PROGRAMMING;

LOGIC CIRCUITS;

EID: 0031337017     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Liu, T., W. K. Huang and F. Lombardi, "Testing of Uncustomized Segmented Channel FPGAs, " 3rd ACM/SIGADA int. Symp. on FP-GAs, pp.125-131, 1995.
2. Huang, W. K. and F. Lombardi, "The General Technique for Testing FPGAs Arrays, " Proc. of VTS '96, pp. 450-455, 1996.
3. Stroud, C. ET al, "Evaluation of FPGA Resources for Built-in Self-Test of Programmable Logic Blocks, " Proc. of 4th ACM/SIGDA Int. Symp. on FPGAs, pp. 107-113, 1996.
4. Stroud, C. et al, "Built-in Self-Test of Logic Blocks in FPGAs (Finally, A Free Lunch, BIST Without overhead, " Proc. of VTS'96, pp. 387392, 1996.
5. Xilinx Inc., Programmable Gate Array Data Book, San Jose, 1991.
6. Huang, W. K., X. T. Chen and F. Lombardi, "On the Diagnosis of Programmable Interconnections: Theory and Applications, " Proc. of VTS '96, pp. 204-209, 1996.