Low-power coding for networks-on-chip with virtual channels

Journal of Low Power Electronics

Volumn 5, Issue 1, 2009, Pages 77-84

  García Ortiz, Alberto ^a   Indrusiak, Leandro S ^b   Murgan, Tudor ^b   Glesner, Manfred ^b  

^a Darmstadt University of Technology ^*  (Spain)

^b DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

Low Power Coding; Network on Chip; Virtual Channel

Indexed keywords

BINARY ALLOYS; CESIUM ALLOYS; ELECTRIC POWER UTILIZATION; LOW POWER ELECTRONICS; NETWORK CODING; QUALITY OF SERVICE;

EXPERIMENTAL SIMULATIONS; LOW POWER; NETWORKS ON CHIPS; POWER REDUCTIONS; PROPOSED ARCHITECTURES; VIRTUAL CHANNELS;

NETWORK-ON-CHIP;

EID: 67649207711     PISSN: 15461998     EISSN: 15462005     Source Type: Journal    
DOI: 10.1166/jolpe.2009.1006     Document Type: Conference Paper

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