A robust edge encoding technique for energy-efficient multi-cycle interconnect

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2007, Pages 68-73

  Seo, Jae Sun ^a   Sylvester, Dennis ^a   Blaauw, David ^a   Kaul, Himanshu ^b   Krishnamurthy, Ram ^b  

^a The Department of Civil and Environmental Engineering   (United States)

^b INTEL RESEARCH   (United States)

Author keywords

Encoding; Interconnect; Multi cycle interconnect; Repeaters

Indexed keywords

DESYNCHRONIZING; EDGE ENCODING; MULTI CYCLE INTERCONNECT;

ENCODING (SYMBOLS); ENERGY EFFICIENCY; ENERGY UTILIZATION; LARGE SCALE SYSTEMS; SYSTEMS ANALYSIS; TELECOMMUNICATION REPEATERS;

EDGE DETECTION;

EID: 36949017447     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1283780.1283796     Document Type: Conference Paper

References (12)

1. R. Arunachalam, et. al., "Optimal shielding/spacing metrics for low power design," Proc. of IEEE Computer Society Annual Symposium on VLSI, pp. 167-172, 2003.
2. S. Wong, et. al., "An empirical three-dimensional crossover capacitance model for multilevel interconnect VLSI circuits," IEEE Transactions on Semiconductor Manufacturing, Vol. 13, pp. 219-227, 2000.
3. http://www.eas.asu.edu/~ptm/interconnect.html
4. K. Nose, and T. Sakurai, "Two schemes to reduce interconnect delays in bi-directional and uni-directional buses," Symposium on VLSI Circuits Dig. Tech. Papers, pp. 193-194, 2001.
5. K. Hirose and H. Yasuura, "A bus delay reduction technique considering crosstalk," Proc. of DATE, pp.441-445, 2000.
6. M. Khellah, et. al., "A Skewed repeater bus architecture for on-chip energy reduction in microprocessors," Proc. of International Conference on Computer Design, pp. 253-257, 2005.
7. A.B. Kahng, S. Muddu and E. Sarto, "Interconnect optimization strategies for high-performance VLSI designs," Proc. of International Conference on VLSI Design, pp. 464-469, 1999.
8. M. Khellah, et. al., "Static pulsed bus for on-chip interconnects," Symposium on VLSI Circuits Dig. Tech. Papers, pp. 78-79, 2002.
9. H. Deogun, et. al., "A dual-Vdd boosted pulsed bus technique for low power and low leakage operation," Proc. of ISLPED, pp. 73-78, 2006.
10. H. Kaul, et. al., "Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, pp. 1225-1238, 2005.
11. A. B. Kahng, et. al., "On Switch Factor Based Analysis of Coupled RC Interconnects," Proc. of DAC, pp. 79-84, 2000.
12. K. Bernstein, et. al, "Design and CAD challenges in sub-90 nm CMOS Technologies," Proc. of ICCAD, pp. 129-136, 2003.