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Volumn , Issue , 2007, Pages 977-982

A multi-objective evolutionary algorithm based optimization model for network-on-chip synthesis

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; CONFORMAL MAPPING; MICROPROCESSOR CHIPS; MULTIOBJECTIVE OPTIMIZATION; REUSABILITY;

EID: 34548137799     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ITNG.2007.10     Document Type: Conference Paper
Times cited : (31)

References (17)
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    • A. D. Pimentel, S. Polstra, F. Terpstra, A. W. van Halderen, J. E. Coffland, and L. O. Hertzberger. Towards efficient design space exploration of heterogeneous embedded media systems. In E. Deprettere, J. Teich, and S. Vassiliadis, editors, Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, volume 2268 of LNCS, Springer-Verlag, 2002, pp.7-73.
    • (2002) LNCS , vol.2268 , pp. 7-73
    • Pimentel, A.D.1    Polstra, S.2    Terpstra, F.3    van Halderen, A.W.4    Coffland, J.E.5    Hertzberger, L.O.6
  • 4
    • 0033318858 scopus 로고    scopus 로고
    • Multi-objective evolutionary algorithms: A comparative case study and the strength pareto approach
    • Nov
    • E. Zitzler and L. Thiele. "Multi-objective evolutionary algorithms: A comparative case study and the strength pareto approach". IEEE Transactions on Evolutionary Computation, 4(3), Nov. 1999, pp. 257-271.
    • (1999) IEEE Transactions on Evolutionary Computation , vol.4 , Issue.3 , pp. 257-271
    • Zitzler, E.1    Thiele, L.2
  • 5
    • 84954421164 scopus 로고    scopus 로고
    • Energy-aware mapping for tile-based NoC architectures under performance constraints
    • Jan
    • J. Hu and R. Marculescu. " Energy-aware mapping for tile-based NoC architectures under performance constraints". In Asia & South Pacific Design Automation Conference, Jan. 2003.
    • (2003) Asia & South Pacific Design Automation Conference
    • Hu, J.1    Marculescu, R.2
  • 6
    • 84893760422 scopus 로고    scopus 로고
    • Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
    • J. Hu and R. Marculescu "Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures," in Proc. DATE'03,2003, pp. 688-693.
    • (2003) Proc. DATE'03 , pp. 688-693
    • Hu, J.1    Marculescu, R.2
  • 7
    • 0034474790 scopus 로고    scopus 로고
    • Efficient Exploration of the SoC Communication Architecture Design Space
    • K. Lahiri, A. Raghunathan, and S. Dey, "Efficient Exploration of the SoC Communication Architecture Design Space," in Proc. IEEE/ACM ICCAD'00, 2000, pp. 424-430.
    • (2000) Proc. IEEE/ACM ICCAD'00 , pp. 424-430
    • Lahiri, K.1    Raghunathan, A.2    Dey, S.3
  • 10
    • 0036149420 scopus 로고    scopus 로고
    • Networks on Chips: A New SoC Paradigm
    • January
    • Luca Benini and Giovanni De Micheli, "Networks on Chips: A New SoC Paradigm". IEEE Computer, January 2002, pp. 70-78.
    • (2002) IEEE Computer , pp. 70-78
    • Benini, L.1    Micheli, G.D.2
  • 12
    • 3042565282 scopus 로고    scopus 로고
    • A power and performance model for network-on-chip architectures
    • Feb. 16-20
    • N. Banerjee, P. Vellanki, and K. S. Chatha, "A power and performance model for network-on-chip architectures.", In Design, Automation and Test in Europe, Feb. 16-20, 2004, pp. 1250-1255.
    • (2004) Design, Automation and Test in Europe , pp. 1250-1255
    • Banerjee, N.1    Vellanki, P.2    Chatha, K.S.3
  • 13
    • 84948696213 scopus 로고    scopus 로고
    • A Network on Chip Architecture and Design Methodology
    • April
    • S. Kumar et al., "A Network on Chip Architecture and Design Methodology," in Proc. ISVLSI'02, April 2002, pp. 105-112.
    • (2002) Proc. ISVLSI'02 , pp. 105-112
    • Kumar, S.1
  • 15
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    • A two-step genetic algorithm for mapping task graphs to a network on chip architecture
    • Sept. 1-6
    • T. Lei and S. Kumar, "A two-step genetic algorithm for mapping task graphs to a network on chip architecture.", In Euro micro Symposium on Digital Systems Design, Sept. 1-6, 2003.
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  • 16
    • 0036053347 scopus 로고    scopus 로고
    • Analysis of Power Consumption on Switch Fabrics in Network Routers
    • June
    • T. T. Ye, L. Benini, and G. D. Micheli, "Analysis of Power Consumption on Switch Fabrics in Network Routers," in Proc. DAC '02, June, 2002, pp.524-529.
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    • Ye, T.T.1    Benini, L.2    Micheli, G.D.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.