Ten years of building broken chips:Physics and engineering of inexact computing

Transactions on Embedded Computing Systems

Volumn 12, Issue 2 SUPPL., 2013, Pages

  Palem, Krishna ^a,b   Lingamneni, Avinash ^c,d  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b RICE UNIVERSITY   (United States)

^c Rice University   (United States)

^d CSEM   (Switzerland)

Author keywords

Co design; EDA; Energy accuracy trade off; Inexact circuit design; Low power energy; Moore's law; Probabilistic CMOS; VLSI design

Indexed keywords

CO-DESIGNS; EDA; ENERGY-ACCURACY TRADE-OFFS; INEXACT CIRCUIT DESIGNS; LOW POWER/ENERGY; MOORE'S LAW; VLSI DESIGN;

HARDWARE; INTEGRATED CIRCUIT MANUFACTURE; INVESTMENTS; LANDFORMS; SEMICONDUCTOR GROWTH;

DESIGN;

EID: 84891115100     PISSN: 15399087     EISSN: 15583465     Source Type: Journal    
DOI: 10.1145/2465787.2465789     Document Type: Article

References (71)

1. Akgul, B. E. S., Chakrapani, L. N., Korkmaz, P., and Palem, K. V. 2006. Probabilistic CMOS technology: A survey and future directions. In Proceedings of the IFIP International Conference on VLSI. 1-6.
2. Banerjee, N., Karakonstantis, G., and Roy, K. 2007. Process variation tolerant low power DCT architecture.In Proceedings of the Design, Automation and Test in Europe Conference. 630-635.
3. ACM Transactions on Embedded Computing Systems, Vol. 12, No. 2s, Article 87, Publication date: May 2013.
4. Boltzmann, L. and Brush, S. 1995. Lectures on Gas Theory, English translation by S.G. Brush. Dover Publications, Mineola, NY.
5. Boole, G. 1847. The mathematical analysis of logic: Being an essay towards a calculus of deductive reasoning.
6. Chakrapani, L. N., Korkmaz, P., Akgul, B. E. S., and Palem, K. V. 2007. Probabilistic system-on-a-chip architectures. ACM Trans. Design Autom. Electron. Syst. 12, 3, 1-28.
7. Chakrapani, L. N., Muntimadugu, K. K., Lingamneni, A., George, J., and Palem, K. V. 2008. Highly energy and performance efficient embedded computing through approximately correct arithmetic: A mathematical foundation and preliminary experimental validation. In Proceedings of the IEEE/ACM International Conference on Compilers, Architectures and Synthesis for Embedded Systems. 187-196.
8. Chakrapani, L. N. B. and Palem, K. V. 2008. A probabilistic boolean logic and its meaning. Tech. rep. TR08- 05, Rice University, Department of Computer Science, Houston, TX.
9. Chang, I. J., Mohapatra, D., and Roy, K. 2009. A voltage-scalable and process variation resilient hybrid sram architecture for mpeg-4 videoprocessors. In Proceedings of the Design Automation Conference. 670-675.
10. Cheemalavagu, S., Korkmaz, P., and Palem, K. V. 2004. Ultra low-energy computing via probabilistic algorithms and devices: CMOS device primitives akrishna v palemnd the energy-probability relationship. In Proceedings of the International Conference on Solid State Devices and Materials. 402-403.
11. Cheemalavagu, S., Korkmaz, P., Palem, K. V., Akgul, B. E. S., and Chakrapani, L. N. 2005. A probabilistic CMOS switch and its realization by exploiting noise. In Proceedings of the IFIP International Conference on VLSI-SoC. 452-457.
12. Chippa, V. K., Mohapatra, D., Raghunathan, A., Roy, K., and Chakradhar, S. T. 2010. Scalable effort hardware design: Exploiting algorithmic resilience for energy efficiency. In Proceedings of the Design Automation Conference. 555-560.
13. Cho, M., Schlessman, J., Wolf, W., and Mukhopadhyay, S. 2009. Accuracy- aware sram: A reconfigurable low power sram architecture for mobile multimedia applications. In Proceedings of the Asia and South Pacific Design Automation Conference. 823-828.
14. De Micheli, G. 1994. Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York, NY.
15. Ernst,D., Kim, N. S.,Das, S., Pant, S., Rao, R., Pham, T., Ziesler, C., Blaauw,D., Austin, T., Flautner,K., and Mudge, T. 2003. Razor: A low-power pipeline based on circuit-level timing speculation. In Proceedings of the IEEE/ACM International Symposium on Microarchitecture. 7-18.
16. Faggin, F. and Hoff, M. E. 1972. Standard parts and custom design merge in a four-chip processor kit. Electron. Mag.
17. Gell-Mann, M. 1997. Trying to make a reliable computer out of unreliable parts.
18. George, J., Marr, B., Akgul, B. E. S., and Palem, K. V. 2006. Probabilistic arithmetic and energy efficient embedded signal processing. In Proceedings of the IEEE/ACM International Conference on Compilers, Architectures and Synthesis for Embedded Systems. 158-168.
19. Gibbs, J. 1902. Elementary Principles in Statistical Mechanics. Scribner, New York, NY.
20. Gyger, S., Corbaz, A., and Beuchat, P.-A. 2009. Hardware development kit for systems based on an icyflex processor. CSEM Scientific and Tech. rep.
21. Hegde, R. and Shanbhag, N. R. 1999. Energy-efficient signal processing via algorithmic noise-tolerance. In Proceedings of the International Symposium on Low Power Electronics and Design. 30-35.
22. Heinig, A., Mooney, V. J., Schmoll, F., Marwedel, P., Palem, K. V., and Engel, M. 2012. Classification-based improvement of application robustness and quality of service in probabilistic computer systems. In Proceedings of the Architecture of Computing Systems Conference. 1-12.
23. Hennessy, J. L. and Patterson, D. A. 2003. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers Inc., Burlington, MA.
24. Jonietz, E. 2008. Probabilistic chips. Technol. Rev. MIT, Cambridge, MA.
25. Karakonstantis, G., Panagopoulos, G., and Roy, K. 2010. Herqules: System level cross-layer design exploration for efficient energy-quality trade-offs. In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design. 117-122.
26. Karp, R. 1977. Probabilistic analysis of partitioning algorithms for the traveling-salesman problem in the plane.Math. Oper. Res. 2, 3, 209-224.
27. Kaul, H., Anders, M., Mathew, S., Hsu, S., Agarwal, A., Krishnamurthy, R., and Borkar, S. 2008. A 320 mv 56 μw 411 gops/watt ultra-low voltage motion estimation accelerator in 65 nm cmos. IEEE J. Solid-State Circuits.ACM Transactions on Embedded Computing Systems, Vol. 12, No. 2s, Article 87, Publication date: May 2013.
28. Kedem, Z. M., Mooney, V. J., Muntimadugu, K. K., Palem, K. V., Devarasetty, A., and Parasuramuni, P. D. 2010. Optimizing energy to minimize errors in dataflow graphs using approximate adders. In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems. 177-186.
29. Kedem, Z. M., Mooney, V. J., Muntimadugu, K. K., and Palem, K. V. 2011. An approach to energy-error tradeoffs in approximate ripple carry adders. In Proceedings of the International Symposium on Low Power Electronics and Design. 211-216.
30. Kim, S. H., Mukohopadhyay, S., andWolf,W. 2009. Experimental analysis of sequence dependence on energy saving for error tolerant image processing. In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design.
31. Kish, L. B. 2002. End of Moore's law: Thermal (noise) death of integration in micro and nano electronics. Physics Lett. A 305, 144-149.
32. Korkmaz, P. 2007. Probabilistic cmos (PCMOS) in the nanoelectronics regime. Ph.D. thesis, Georgia Institute of Technology, Atlante, GA.
33. Korkmaz, P., Akgul, B. E. S., Palem, K. V., and Chakrapani, L. N. 2006. Advocating noise as an agent for ultra low-energy computing: Probabilistic CMOS devices and their characteristics. Japan. J. App. Physics 45, 4B, 3307-3316.
34. Kurdahi, F. J., Eltawil, A., Yi, K., Cheng, S., and Khajeh, A. 2010. Low-power multimedia system design by aggressive voltage scaling. IEEE Trans. VLSI Syst. 18, 5, 852-856.
35. Landauer, R. 1961. Irreversibility and heat generation in the computing process. IBM J. Res. Develop. 3. 183-191.
36. Leem, L., Cho, H., Bau, J., Jacobson, Q., and Mitra, S. 2010. Ersa: Error resilient system architecture for probabilistic applications. In Proceedings of the Design, Automation and Test in Europe Conference. 1560-1565.
37. Lingamneni, A., Enz, C. C., Nagel, J.-L., Palem, K. V., and Piguet, C. 2011a. Energy parsimonious circuit design through probabilistic pruning. In Proceedings of the Design, Automation and Test in Europe Conference. 764-769.
38. Lingamneni, A., Enz, C. C., Palem, K. V., and Piguet, C. 2011b. Parsimonious circuit design for error-tolerant applications through probabilistic logic minimization. In Proceedings of the International Workshop on Power And Timing Modeling, Optimization and Simulation. 204-213.
39. Lingamneni, A., Muntimadugu, K. K., Enz, C. C., Karp, R. M., Palem, K. V., and Piguet, C. 2012. Algorithmic methodologies for ultra-efficient inexact architectures for sustaining technology scaling. In Proceedings of the ACM International Conference on Computing Frontiers.
40. Lingamneni, A., Enz, C. C., Palem, K. V., and Piguet, C. 2013. Synthesizing parsimonious inexact circuits through probabilistic design techniques. ACM Trans. Embed. Comput. Syst. (spl. issue on Probabilistic Embedded Computing).
41. Ludwig, J., Nawab, S., and Chandrakasan, A. 1995. Low power filtering using approximate processing for DSP applications. In Proceedings of the IEEE Custom Integrated Circuits Conference. 185-188.
42. Mauchly, J. and Eckert, J. 1947. Electrical numerical integrator and calculator. U.S. Patent 3120606, filed June 26, 1947 and issued Feb 4, 1964.
43. Maxwell, J. C. 1871. Theory of Heat, Greenword Press, Westport, CT.
44. McCulloch, W. and Pitts, W. 1943. A logical calculus of the ideas immanent in nervous activity. Bull. Math. Biophysics 7, 115-133.
45. Meindl, J., Naeemi, A., Bakir, M., and Murali, R. 2010. Nanoelectronics in retrospect, prospect and principle. In Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). 31-35.
46. Minsky, M. 1967. Computation: Finite and Infinite Machines. Prentice-Hall, Inc., Englewood Cliffs, NJ.
47. Mohapatra, D., Karakonstantis, G., and Roy, K. 2009. Significance driven computation: A voltage-scalable, variation-aware, quality-tuning motion estimator. In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design. 195-200.
48. Moore, E. and Shannon, C. 1956a. Reliable circuits using less reliable relays I. J. Franklin Instit. 262, 191-208.
49. Moore, E. and Shannon, C. 1956b. Reliable circuits using less reliable relays II. J. Franklin Instit. 262, 281-297.
50. Moore, G. E. 1965. Cramming more components onto integrated circuits. Electron. Mag. 38, 8.
51. Mudge, T. 2001. Power: A first-class architectural design constraint. Computer 34, 4, 52-57.
52. Narayanan, S., Sartori, J., Kumar, R., and Jones, D. L. 2010. Scalable stochastic processors. In Proceedings of the Design, Automation and Test in Europe Conference. 335-338.
53. Nikolic, K., Sadek, A., and Forshaw, M. 2001. Architectures for reliable computing with unreliable nanodevices. In Proceedings of the IEEE Conference on Nanotechnology. 254-259.
54. Palem, K. V. 2003a. Energy aware algorithm design via probabilistic computing: From algorithms and models to Moore's law and novel (semiconductor) devices. In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems. 113-116.
55. Palem, K. V. 2003b. Proof as experiment: Probabilistic algorithms from a thermodynamic perspective. In Proceedings of the International Symposium on Verification (Theory and Practice).
56. Palem, K. V. 2005. Energy aware computing through probabilistic switching: A study of limits. IEEE Trans. Comput. 54, 9, 1123-1137 (abridged form appeared as K.V. Palem, Energy aware computing through randomized switching, Tech. rep. GIT-CC-03-16, Georgia Inst. of Technology.
57. Palem, K. V., Cheemalavagu, S., Korkmaz, P., and Akgul, B. E. 2005. Probabilistic and introverted switching to conserve energy in a digital system. U.S. Patent 20050240787, filed April 27, 2005 and issued October 27, 2005.
58. Palem, K. V., Akgul, B. E. S., and George, J. 2006. Variable scaling for computing elements. Invention Disclosure.
59. Palem, K. V., Chakrapani, L. N., Kedem, Z. M., Lingamneni, A., and Muntimadugu, K. K. 2009a. Sustaining moore's law in embedded computing through probabilistic and approximate design: Retrospects and prospects. In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems. 1-10.
60. Palem, K. V., Korkmaz, P., Yeo, K.-S., and Kong, Z.-H. 2009b. Probabilistic cmos (pcmos) logic for nanoscale circuit design. In Proceedings of the International Solid State Circuits Conference: Advanced Solid-State Circuits Forum.
61. Palem, K. V. and Lingamneni, A. 2012. What to do about the end of moore's law, probably! In Proceedings of the 49th Design Automation Conference.
62. Rabin, M. O. 1963. Probabilistic automata. Inform. Control 6, 230-245.
63. Randall, V. A. 2006. A lost interview with ENIAC co-inventor J. Presper Eckert.
64. Sartori, J., Sloan, J., and Kumar, R. 2011. Stochastic computing: Embracing errors in architecture and design of processors and applications. In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, 135-144.
65. Shannon, C. 1937. A symbolic analysis of relay and switching circuits. M.S. thesis, Massachusetts Institute of Technology, Cambridge, MA.
66. Solovay, R. and Strassen, V. 1977. A fast monte-carlo test for primality. SIAM J. Comput.
67. Szilard, L. 1929. Reduction in entropy of a thermodynamic system caused by the interference of intelligent beings. Z. Physik 53, 840-856.
68. Turing, A. M. 1936. On computable numbers, with an application to the entscheidungsproblem. In Proceedings of the London Mathematical Society 42, 230-265.
69. Ulam, S., Richtmyer, R. D., and von Neumann, J. 1947. Statistical methods in neutron diffusion. Los Alamos Scientific Laboratory report LAMS551.
70. von Neumann, J. 1956. Probabilistic logics and the synthesis of reliable organisms from unreliable components. In Automata Studies, C. E. Shannon and J. McCarthy Eds., Priceton Univ. Press, Princeton, N.J.
71. Zuse, K. 1993. Der Computer. Mein Lebenswerk 3rd Ed. Number 978-3-540-56292-4. Springer-Verlag.