Demystifying data-driven and pausible clocking schemes

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2007, Pages 175-185

  Mullins, Robert ^a   Moore, Simon ^a  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; FAILURE ANALYSIS;

ASYNCHRONOUS INTERFACE; CLOCKING SCHEMES; DATA DRIVEN; DESIGN STYLES; FAILURE RATE; ON-CHIP BUS; ON-CHIP NETWORKS; PAUSIBLE CLOCKING; SYNCHRONOUS DESIGNS; VLSI SYSTEM;

CLOCKS;

EID: 84886888538     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: 10.1109/async.2007.15     Document Type: Conference Paper

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