Priority arbiters

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2000, Pages 128-137

  Bystrov, A ^a   Kinniment, D J ^a   Yakovlev, A ^a  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL FEATURES; ASYNCHRONOUS DESIGN; CONTROL FLOWS; DATA PATHS; SHARED RESOURCES; SPEED-INDEPENDENT; TREE STRUCTURES;

DATA PROCESSING; TOPOLOGY;

TREES (MATHEMATICS);

EID: 77957944949     PISSN: 15228681     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2000.836990     Document Type: Conference Paper

References (10)

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2. Clements, A.: 'Microprocessor system design', 3rd edition, Int. Thomson Publishers, 1997.
3. Del Corso, D., Kirrmann, H., Nicoud, J.D.: 'Microcomputer buses and links', Academic Press, 1986.
4. Yakovlev, A.: 'Designing arbiters using Petri nets', 1995 Israel Workshop on Asynchronous VLSI, 1995, VLSI Systems Research Center, Israel Institute of Technology, Haifa, Israel, pp. 179-201.
5. Muller D.E., Bartky: 'A theory of asynchronous circuits', in Proceedings of International Symposium on the Theory of Switching, April 1959, Harvard University Press, pp. 204-243.
6. Martin, A.J.: 'Collected papers on asynchronous VLSI design', Technical Report, Caltech-CS-TR-90-09, Dept. of Computer Science, California Institute of technology, 1990.
7. Bystrov, A., Yakovlev, A.: 'Ordered Arbiters', IEE Electronics Letters, 27 May 1999, vol. 35, No 11, pp. 877-879.
8. Kinniment, D.J., Woods, J.V.: 'Synchronisation and arbitration circuits in digital systems', Proc. IEE, Oct 1976, Vol 123 No 10, pp. 961-966.
9. Josephs MB, Yantchev J. CMOS Design of the Tree Arbiter Element. IEEE Trans. on VLSI Systems, 1996, Vol. 4, No. 4, pp. 472-476.
10. Yakovlev, A., Petrov, A., Lavagno, L. A Low Latency Asynchronous Arbitration Circuit. IEEE Trans. on VLSI Systems, 1994, vol. 2, No. 3, pp. 372-377.