CMOS design of the tree arbiter element

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 4, Issue 4, 1996, Pages 472-476

  Josephs, Mark B ^a   Yantchev, Jelio T ^b  

^a LONDON SOUTH BANK UNIVERSITY   (United Kingdom)

^b UNIVERSITY OF ADELAIDE   (Australia)

Author keywords

Analog difference circuit; Arbiters; Asynchronous interaction; CMOS design; Flip flop metastable region; Glitch phenomenon; Mutual exclusion element; Quick return linkage; Speed independent circuit; Tree arbiter element

Indexed keywords

COMPUTER SIMULATION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; NETWORK PROTOCOLS; RESOURCE ALLOCATION; VLSI CIRCUITS;

ANALOG DIFFERENCE CIRCUIT; ARBITERS; FLIP FLOP METASTABLE STATE; MUTUAL EXCLUSION ELEMENT; QUICK RETURN LINKAGE; TREE ARBITER ELEMENT;

CMOS INTEGRATED CIRCUITS;

EID: 0030388591     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.544412     Document Type: Article

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