Synchro-tokens: A deterministic GALS methodology for chip-level debug and test

IEEE Transactions on Computers

Volumn 54, Issue 12, 2005, Pages 1532-1546

  Heath, Matthew W ^a   Burleson, Wayne P ^b   Harris, Ian G ^c  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF MASSACHUSETTS   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Debug; GALS; Globally asynchronous locally synchronous; Nondeterminism; SoC; Test

Indexed keywords

BUFFER STORAGE; COMPUTER CIRCUITS; COMPUTER NETWORKS; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PERFORMANCE;

CHIP-LEVEL DEBUG; CLOCK CYCLES; DATA CHANNELS; GLOBALLY-ASYNCHRONOUS LOCALLY-SYNCHRONOUS (GALS); SYNCHRO-TOKENS;

COMPUTER DEBUGGING;

EID: 30344437884     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2005.203     Document Type: Article

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