A monolithic digital clock-generator for on-chip clocking of custom DSP's

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 5, 1996, Pages 700-706

  Nilsson, Peter ^b,c,d   Torkelson, Mats ^a,b,e,f,g,h  

^a IEEE

^b LUND UNIVERSITY   (Sweden)

^c LUND INSTITUTE OF TECHNOLOGY   (Sweden)

^d Digital Signal Processing Group

^e ETH ZURICH   (Switzerland)

^f Willi Studer AG   (Switzerland)

^g UNIVERSITY OF CALIFORNIA   (United States)

^h ERICSSON RADIO SYSTEMS AB   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SIMULATION; DATABASE SYSTEMS; DECODING; INTEGRATED CIRCUIT LAYOUT; NEURAL NETWORKS; PROLOG (PROGRAMMING LANGUAGE); PROM; RANDOM ACCESS STORAGE; TABLE LOOKUP;

CRITICAL PATH CIRCUITS; HARDWARE DICTIONARY PROCESSORS; TRANSLATION LOOK ASIDE BUFFERS; TWO DIMENSIONAL DECODING;

ASSOCIATIVE STORAGE;

EID: 0030149831     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.509852     Document Type: Article

References (12)

1. Electronic Industries Association, "Dual-mode subscriber equipment - Network equipment compatibility specification," Interim Standard 54, Dec. 1989.
2. A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, "Low-power CMOS digital design," IEEE J. Solid-State Circuits, vol. 27, pp. 473-484, Apr. 1992.
3. D. L. Chen, "Designing on-chip clock generators," IEEE Circuits Devices Mag., vol. 8, pp. 32-36, July 1992.
4. C. B. Shung et al., "An integrated CAD system for algorithm-specific IC design," IEEE Trans. Computer-Aided Design, vol. 10, pp. 447-463, Apr. 1991.
5. R. Jain et al., "Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using a computer-aided design system," IEEE J. Solid-State Circuits, vol. SC-21, pp. 73-85, Feb. 1986.
6. S. Tanaka et al., "An adaptive equalizing maximum likelihood decoding lsi for magnetic recording systems," in Proc. 1993 IEEE Int. Solid-State Circuits Conf., 1993, pp. 220, 221, 292.
7. A. Fettweis, "Wave digital filters: Theory and practice," Proc. IEEE, vol. 74, pp. 270-327, Feb. 1986.
8. T. H. Hu and P. R. Gray, "A monolithic 480 mb/s parallel AGC/ decision/clock-recovery circuit in 1.2-μm CMOS," IEEE J. Solid-State Circuits, vol. 28, pp. 1314-1320, Dec. 1993.
9. J. K. Greason, I. A. Young, and K. L. Wong, "A PLL clock generator with 5 to 110 MHz of lock range for microprocessors," IEEE J. Solid-State Circuits, vol. 27, pp. 1599-1607, Nov. 1992.
10. G. M. Jacobs and R. W. Brodersen, "A fully asynchronous digital signal processor using self-timed circuits," IEEE J. Solid-State Circuits, vol. 25, pp. 1526-1537, Dec. 1990.
11. R. F. Lyon, "Two's complement pipeline multipliers," IEEE Trans. Commun., vol. 24, pp. 418-425, Apr. 1976.
12. A. Waizman, "A delay line loop for frequency synthesis of de-skewed clock," in Proc. 1994 IEEE Int. Solid-State Circuits Conf., 1994, pp. 298-299.