GALS at ETH Zurich: Success or failure?

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn 2006, Issue , 2006, Pages 150-159

  Gürkaynak, Frank K ^a   Oetiker, Stephan ^a   Kaeslin, Hubert ^a   Felber, Norbert ^a   Fichtner, Wolfgang ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CRYPTOGRAPHY; LOGIC CIRCUITS; LOGIC DESIGN; SILICON; SYNCHRONOUS GENERATORS;

CRYPTOGRAPHIC SECURITY; GLOBALLY-ASYNCHRONOUS LOCALLY-SYNCHRONOUS (GALS); HIERARCHICAL DESIGN FLOWS; MULTI-POINT INTERCONNECTS;

ASYNCHRONOUS MACHINERY;

EID: 33749589398     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2006.18     Document Type: Conference Paper

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