High speed externally asynchronous/internally clocked systems

IEEE Transactions on Computers

Volumn 46, Issue 7, 1997, Pages 824-829

  VanScheik, W S ^a   Tinder, R F ^b  

^a Silicon Systems Inc   (United States)

^b Washington State University   (United States)

Author keywords

Asynchronous controllers; Delay insensitive modules; Domino logic modules; Dynamic logic memory; Internally clocked systems; Locally clocked controllers; Pausable clocked systems

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; CONTROL SYSTEM SYNTHESIS; LOGIC CIRCUITS; STORAGE ALLOCATION (COMPUTER);

DELAY INSENSITIVE MODULES; EXTERNALLY ASYNCHRONOUS/INTERNALLY CLOCKED (EAIC) SYSTEMS; PAUSABLE CLOCKED SYSTEMS; SOFTWARE PACKAGE PSPICE;

TIMING CIRCUITS;

EID: 0031188225     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.599904     Document Type: Article

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