Reduction of instantaneous power by ripple scan clocking

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2005, Pages 271-276

  Joshi, Kirti ^a   MacDonald, Eric ^a  

^a 500 W University Avenue   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATED TEST EQUIPMENT; BATTERY-POWERED APPLICATIONS; CMOS TECHNOLOGY; EXPONENTIAL INCREASE; FLIP-FLOP DESIGNS; INSTANTANEOUS POWER; MANUFACTURING TESTS; SUPPLY VOLTAGES;

ABILITY TESTING; BUILT-IN SELF TEST; CLOCKS; CMOS INTEGRATED CIRCUITS;

INTEGRATED CIRCUIT TESTING;

EID: 84886535973     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2005.71     Document Type: Conference Paper

References (18)

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