A token scan architecture for low power testing

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 660-669

  Huang, Tsung Chu ^a   Lee, Kuen Jong ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; FLIP FLOP CIRCUITS; TIMING CIRCUITS;

TOKEN SCAN ARCHITECTURE;

INTEGRATED CIRCUIT TESTING;

EID: 0035684001     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)

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