MD-SCAN method for low power scan testing

Proceedings of the Asian Test Symposium

Volumn 2002-January, Issue , 2002, Pages 80-85

  Yoshida, T ^a   Watari, M ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

Circuit synthesis; Circuit testing; Clocks; Costs; Flip flops; Large scale integration; Power dissipation; Power supplies; Semiconductor device manufacture; Voltage

Indexed keywords

CLOCKS; COSTS; ELECTRIC LOSSES; ELECTRIC POTENTIAL; ELECTRONIC EQUIPMENT TESTING; ENERGY DISSIPATION; FLIP FLOP CIRCUITS; LSI CIRCUITS; MANUFACTURE; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE TESTING; SEMICONDUCTOR DEVICES;

CIRCUIT SYNTHESIS; CIRCUIT TESTING; CRITICAL PROBLEMS; POWER SUPPLY; POWER SUPPLY VOLTAGE; SEMICONDUCTOR MANUFACTURING; SHIFT OPERATIONS; TESTING METHOD;

INTEGRATION TESTING;

EID: 0142206015     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2002.1181690     Document Type: Conference Paper

References (8)

1. E. Larsson, Z. Peng, "Test Scheduling and Scan-Chain Division Under Power Constraint", Asian Test Symp. , pp. 259-264, November 2001.
2. R. M. Chou, K. K. saluja, V. D. Agrawal, "Scheduling Test for VLSI Systems under Power Constraints", Transaction on Very Large Scale Integration Systems, Vol. 5, No. 2, pp. 175-185, June 1997.
3. J. Saxena, K. M. Butler, L. Whetsel, "An Analysis of Power Reduction Techniques in Scan Testing", International Test Conference, pp. 670-677, 2001.
4. T. C. Huang, K. J. Lee, "A Token Scan Architecture for Low Power Testing", International Test Conference, pp. 660-669, 2001.
5. Y. Bonhomme, P. Girard, L. Guiller, C. Landra, S. Pravossoudovitch, "A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores", Asian Test Symp. , pp. 253-258, November 2001.
6. N. Nicolici, M. Al-Hashimi, "Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full-Scan Sequential Circuits", Design, Automation and Test in Europe(DATE) Conference, pp. 715-722, March 2000.
7. R. Sankaralingam, B. Pouya, N. A. Touba, "Reducing Power Dissipation during Test using Scan Chain Disable", VLSI Test Symposium, pp. 319-324, April 2001.
8. L. Whetsel, "Adapting Scan Architectures for Low Power Operation", International Test Conference, pp. 863-872, October 2000.