RTL level preparation of high-quality / low-energy / low-power BIST

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 814-823

  Santos, M B ^a   Teixeira, I C ^a   Teixeira, J P ^a   Manich, S ^b   Rodriguez, R ^b   Figueras, J ^b  

^a INESC ID   (Portugal)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTER AIDED NETWORK ANALYSIS; ELECTRIC EXCITATION; ELECTRIC POWER MEASUREMENT; OPTIMIZATION; RANDOM PROCESSES; SWITCHING CIRCUITS; VECTOR QUANTIZATION;

BENCHMARK CIRCUITS; DEFECTS COVERAGE; HIGH QUALITY BUILT-IN SELF TEST; LOW ENERGY BUILT-IN SELF TEST; LOW POWER BUILT-IN SELF TEST; PSEUDO RANDOM TEST EXCITATION; REGISTER TRANSFER LEVEL;

BUILT-IN SELF TEST;

EID: 0036443196     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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