Very low voltage testing of SOI integrated circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 25-30

  MacDonald, E ^a   Touba, N A ^b  

^a IBM MICROELECTRONICS   (United States)

^b The University of Texas at Austin   (United States)

Author keywords

Circuit testing; CMOS integrated circuits; Condition monitoring; Delay effects; Fabrication; History; Integrated circuit testing; Low voltage; Silicon on insulator technology; Switching circuits

Indexed keywords

CHOPPERS (CIRCUITS); CMOS INTEGRATED CIRCUITS; CONDITION MONITORING; DELAY CIRCUITS; FABRICATION; HISTORY; INTEGRATED CIRCUITS; SILICON; SILICON ON INSULATOR TECHNOLOGY; SWITCHING CIRCUITS; VLSI CIRCUITS;

CIRCUIT TESTING; DELAY EFFECTS; FABRICATION PROCESS; LOW VOLTAGES; NORMAL OPERATING CONDITIONS; SILICON-ON- INSULATORS (SOI); TEST TECHNIQUES; VERY LOW VOLTAGE;

INTEGRATED CIRCUIT TESTING;

EID: 84948443928     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011106     Document Type: Conference Paper

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