Impact of Transistor Architecture (Bulk Planar, Trigate on Bulk, Ultrathin-Body Planar SOI) and Material (Silicon or III-V Semiconductor) on Variation for Logic and SRAM Applications

IEEE Transactions on Electron Devices

Volumn 60, Issue 10, 2013, Pages 3298-3304

  Agrawal, Nidhi ^a   Kimura, Yoshie ^b   Arghavani, Reza ^b   Datta, Suman ^a  

^a The Pennsylvania State University   (United States)

^b LAM RESEARCH CORPORATION   (United States)

Author keywords

FinFET; III V compound semiconductor; line edge roughness (LER); sidewall roughness (SWR); SRAM; surface roughness (SR); trigate; UTB SOI

Indexed keywords

FINFET; III-V COMPOUND SEMICONDUCTOR; LINE EDGE ROUGHNESS; SIDEWALL ROUGHNESS; TRIGATE; UTB SOI;

NANOTECHNOLOGY; SILICON; SILICON COMPOUNDS; STATIC RANDOM ACCESS STORAGE; SURFACE ROUGHNESS; TRANSISTORS;

SEMICONDUCTING SILICON;

EID: 84884776123     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2013.2277872     Document Type: Article

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