Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2012, Pages 117-118

  Khakifirooz, A ^a   Cheng, K ^a   Nagumo, T ^b   Loubet, N ^c   Adam, T ^a   Reznicek, A ^a   Kuss, J ^a   Shahrjerdi, D ^f   Sreenivasan, R ^a   Ponoth, S ^a   He, H ^a   Kulkarni, P ^a   Liu, Q ^c   Hashemi, P ^f   Khare, P ^c   Luning, S ^d   Mehta, S ^a   Gimbert, J ^c   Zhu, Y ^f   Zhu, Z ^g   Li, J ^a   Madan, A ^g   Levin, T ^a   Monsieur, F ^c   Yamamoto, T ^b   Naczas, S ^a   Schmitz, S ^a   Holmes, S ^a   Aulnette, C ^e   Daval, N ^e   Schwarzenbach, W ^e   Nguyen, B Y ^e   Paruchuri, V ^a   Khare, M ^a   Shahidi, G ^f   Doris, B ^a   more..

^a IBM RESEARCH   (United States)

^b Renesas   (United States)

^c STMICROELECTRONICS   (Italy)

^d IBM MICROELECTRONICS   (United States)

^e SOITEC   (United States)

^f IBM T J WATSON RESEARCH CENTER   (United States)

^g IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DRIVE CURRENTS; HIGH-PERFORMANCE CMOS; SIGE-ON-INSULATOR; STRAINED-SOI; THIN SOI;

SEMICONDUCTOR INSULATOR BOUNDARIES;

SILICON ON INSULATOR TECHNOLOGY;

EID: 84866546880     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2012.6242489     Document Type: Conference Paper

References (3)

1. K. Cheng, et al., Symp. VLSI Tech., p. 128, 2011.
2. B. Greene, et al., Symp. VLSI Tech., p. 140, 2009.
3. P. Packan, et al., IEDM, p. 659, 2009.