Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2011, Pages

  Radosavljevic, M ^a   Dewey, G ^a   Basu, D ^a   Boardman, J ^a   Chu Kung, B ^a   Fastenau, J M ^b   Kabehie, S ^a   Kavalieros, J ^a   Le, V ^a   Liu, W K ^b   Lubyshev, D ^b   Metz, M ^a   Millard, K ^a   Mukherjee, N ^a   Pan, L ^a   Pillarisetty, R ^a   Rachmady, W ^a   Shah, U ^a   Then, H W ^a   Chau, Robert ^a  

^a INTEL CORPORATION   (United States)

^b IQE INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEVICE ARCHITECTURES; FIN WIDTHS; HIGH QUALITY; HIGH-K GATE DIELECTRICS; INGAAS QUANTUM WELLS; LOGIC APPLICATIONS; LOW POWER; TRIGATE; ULTRA-THIN; ULTRATHIN BODY;

DIELECTRIC DEVICES; DISSOCIATION; ELECTRON DEVICES; ELECTROSTATICS; EQUIPMENT; FINS (HEAT EXCHANGE); SEMICONDUCTING INDIUM; SEMICONDUCTOR QUANTUM WELLS; THREE DIMENSIONAL;

FIELD EFFECT TRANSISTORS;

EID: 84863044285     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2011.6131661     Document Type: Conference Paper

References (5)

1. R.S. Chau et al., SSDM Ext. Abst., pp. 68 (2002).
2. B.S. Doyle et al., VLSI Tech. Dig., pp.133 (2003).
3. Y.Q. Wu et al., IEDM Tech. Dig., pp.13.4 (2009).
4. M. Radosavljevic et al., IEDM Tech. Dig., pp.6.1.1 (2010).
5. M. Radosavljevic et al., IEDM Tech. Dig., pp.13.1 (2009).