Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011

Volumn , Issue , 2011, Pages 45-52

  Saripalli, Vinay ^a   Datta, Suman ^a   Narayanan, Vijaykrishnan ^a   Kulkarni, Jaydeep P ^b  

^a The Pennsylvania State University   (United States)

^b INTEL RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAYED OUTPUT; DYNAMIC ENERGY; FEEDBACK MECHANISMS; INTERBAND; LEAKAGE POWER; LOW POWER; LOW SUPPLY VOLTAGES; NOISE MARGINS; SOURCE-DRAIN; SRAM CELL; SRAM DESIGN; SUBTHRESHOLD; SWITCHING PERFORMANCE; TUNNEL FET; VARIATION MODELS; VARIATION TOLERANCES;

ARCHITECTURE; CELLS; HETEROJUNCTIONS; LINEAR TRANSFORMATIONS; LOGIC DESIGN; MESFET DEVICES; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY;

STATIC RANDOM ACCESS STORAGE;

EID: 79961190330     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANOARCH.2011.5941482     Document Type: Conference Paper

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