Trends on the application of emerging nonvolatile memory to processors and programmable devices

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2013, Pages 101-104

  Torres, Lionel ^a   Brum, Raphael Martins ^a   Cargnini, Luis Vitorio ^a   Sassatelli, Gilles ^a  

^a LIRMM   (France)

Author keywords

Cache Memory; FeRAM; FPGA; Memory in logic; MRAM; NVM; PCM; RRAM

Indexed keywords

FERAM; MEMORY-IN-LOGIC; MRAM; NVM; RRAM;

BUFFER STORAGE; CACHE MEMORY; DATA STORAGE EQUIPMENT; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MAGNETIC STORAGE; PULSE CODE MODULATION; RANDOM ACCESS STORAGE; TECHNOLOGY;

MRAM DEVICES;

EID: 84883433117     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2013.6571792     Document Type: Conference Paper

References (25)

1. (2011) International Technology Roadmap for Semiconductors. [Online]. Available: Http://www.itrs.net/Links/2011ITRS/Home2011.htm
2. N. Bruchon, L. Torres, G. Sassatelli, and G. Cambon, "New nonvolatile FPGA concept using magnetic tunneling junction," in Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on, vol. 00, march 2006, p. 6 pp.
3. Y. Y. Liauw, Z. Zhang, W. Kim, A. Gamal, and S. Wong, "Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International, feb. 2012, pp. 406 -408.
4. M. Liu and W. Wang, "rFPGA: CMOS-nano hybrid FPGA using RRAM components," in Nanoscale Architectures, 2008. NANOARCH 2008. IEEE International Symposium on, june 2008, pp. 93 -98.
5. Y. Guillemenet, "Logique magnétique pour l'exploration d'architectures reconfigurables," PhD Thesis, Univ. Montpellier II, 2011, in French.
6. G. Prenat, M. El Baraji, W. Guo, R. Sousa, L. Buda-Prejbeanu, B. Dieny, V. Javerliac, J.-P. NoziERES, W. Zhao, and E. Belhaire, "CMOS/Magnetic Hybrid Architectures," in Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on, dec. 2007, pp. 190 -193.
7. W. Zhao, E. Belhaire, C. Chappert, B. Dieny, and G. Prenat, "TASMRAM based low power, high speed Run-Time Reconfiguration (RTR) FPGA," ACM Trans on Reconfigurable Techno. and systems, vol. 2, 2009.
8. C. Chen, W. Lee, R. Parsa, S. Chong, J. Provine, J. Watt, R. Howe, H.-S. Wong, and S. Mitra, "Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique," in Design, Automation Test in Europe Conference Exhibition (DATE), 2012, march 2012, pp. 1361 -1366.
9. Y. Zhou, S. Thekkel, and S. Bhunia, "Low power FPGA design using hybrid CMOS-NEMS approach," in Proceedings of the 2007 international symposium on Low power electronics and design, ser. ISLPED '07. New York, NY, USA: ACM, 2007, pp. 14-19.
10. V. Sirigir, K. Alzoubi, D. Saab, F. Kocan, and M. Tabib-Azar, "Ultralow- Power Ultra-fast Hybrid CNEMS-CMOS FPGA," in Field Programmable Logic and Applications (FPL), 2010 International Conference on, 31 2010-sept. 2 2010, pp. 368 -373.
11. W. Zhao, E. Belhaire, C. Chappert, and P. Mazoyer, "Spin transfer torque (STT)-MRAM-based runtime reconfiguration FPGA circuit," ACM Trans. Embed. Comput. Syst., vol. 9, no. 2, pp. 14:1-14:16, Oct. 2009.
12. S. Paul, S. Mukhopadhyay, and S. Bhunia, "Hybrid CMOS-STTRAM non-volatile FPGA: Design challenges and optimization approaches," in Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, ser. ICCAD '08. Piscataway, NJ, USA: IEEE Press, 2008, pp. 589-592.
13. S. Chilstedt, C. Dong, and D. Chen, "Design and evaluation of a carbon nanotube-based programmable architecture," International Journal of Parallel Programming, vol. 37, pp. 389-416, 2009.
14. M. Liu, H. Yang, S. Tanachutiwat, and W. Wang, "FPGA based on integration of carbon nanorelays and CMOS devices," in Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on, july 2009, pp. 61 -64.
15. W. Wang, T. Jing, and B. Butcher, "FPGA based on integration of memristors and CMOS devices," in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 30 2010-june 2 2010, pp. 1963 -1966.
16. J. Cong and B. Xiao, "mrfpga: A novel fpga architecture with memristorbased reconfiguration," Nanoscale Architectures, IEEE International Symposium on, vol. 0, pp. 1-8, 2011.
17. Y. Chen, J. Zhao, and Y. Xie, "3D-NonFAR: Three-dimensional nonvolatile FPGA architecture using phase change memory," in Low- Power Electronics and Design (ISLPED), 2010 ACM/IEEE International Symposium on, aug. 2010, pp. 55 -60.
18. W. Kim, S. I. Park, Z. Zhang, Y. Yang-Liauw, D. Sekar, H. Wong, and S. Wong, "Forming-free nitrogen-doped AlOX RRAM with sub-uA programming current," in VLSI Technology (VLSIT), 2011 Symposium on, june 2011, pp. 22 -23.
19. H. Yoda, S. Fujita, N. Shimomura, E. Kitagawa, K. Abe, K. Nomura, H. Noguchi, and J. Ito, "Progress of STT-MRAM Technology and the Effect on Normally-off Computing Systems," in Electron Devices Meeting, 2012. IEDM Technical Digest. IEEE International, dec. 2012.
20. Y. Guillemenet, L. Torres, G. Sassatelli, N. Bruchon, and I. Hassoune, "A non-volatile run-time FPGA using thermally assisted switching MRAMS," in Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on, sept. 2008, pp. 421 -426.
21. Menta eFPGA. [Online]. Available: Http://menta.fr/efpga-core-ip.html
22. G. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen, "A novel architecture of the 3D stacked MRAM L2 cache for CMPs," in High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium on, feb. 2009, pp. 239 -249.
23. K. Lee and S. Kang, "Development of Embedded STT-MRAM for Mobile System-on-Chips," Magnetics, IEEE Transactions on, vol. 47, no. 1, pp. 131 -136, jan. 2011.
24. A. Jog, A. Mishra, C. Xu, Y. Xie, V. Narayanan, R. Iyer, and C. Das, "Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs," in Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE, june 2012, pp. 243 -252.
25. W. Zhao, L. Torres, L. Cargnini, R. Brum, Y. Zhang, Y. Guillemenet, G. Sassatelli, Y. Lakys, J. Klein, D. Etiemble et al., "High Performance SoC Design Using Magnetic Logic and Memory," in VLSI-SoC: Advanced Research for Systems on Chip. Springer Boston, 2012, pp. 10-33.