Hybrid CMOS-STTRAM non-volatile FPGA: Design challenges and optimization approaches

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2008, Pages 589-592

  Paul, Somnath ^a   Mukhopadhyay, Saibal ^b   Bhunia, Swarup ^a  

^a CASE WESTERN RESERVE UNIVERSITY   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Emerging memory technologies; Non volatile FPGA; STTRAM

Indexed keywords

APPLICATION MAPPINGS; BENCHMARK CIRCUITS; DESIGN CHALLENGES; DYNAMIC POWERS; EMERGING MEMORY TECHNOLOGIES; FPGA DESIGNS; HIGH INTEGRATION DENSITIES; HIGH SPEEDS; HYBRID CMOS; LOW POWERS; NON-VOLATILE FPGA; OPTIMIZATION APPROACHES; OPTIMIZATION TECHNIQUES; RESEARCH EFFORTS; SIMULATION RESULTS; STTRAM;

BENCHMARKING; COMPUTER AIDED DESIGN; DELAY CIRCUITS; DESIGN; NETWORKS (CIRCUITS); OPTIMIZATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 57849141185     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2008.4681636     Document Type: Conference Paper

References (13)

1. M. Hosomi et al, "A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-RAM", IEDM Tech. Dig., pp. 473-476, Dec., 2006.
2. J. Hayakawa et al, "Current-Driven Magnetization Swicthing in CoFeB/MgO/CoFeB Magnetic Tunnel Junctions", Japanese Journal of Applied Physics, 44(41), pp. L1267-L1270, 2005.
3. T. Kawahara et al, "2Mb Spin-Transfer Torque RAM (SPRAM) with Bitby-Bit Bidirectional Current Write and Paralilelizing-Direction Current Read", isscc, 2007.
4. P. Chow et al, "The Design of an SRAM based Field-Programmable Gate Array, Part II: Circuit Design and Layout", IEEE Transactions on VLSI, Vol. 7, pp. 191-197, 1999.
5. N.Bruchon et al, "New non-volatile FPGA concept using Magnetic Tunneling Junction", ISVLSI, 2006.
6. S. Tehrani et al, "Magnetoresistive Random Access Memory Using Magnetic Tunnel Junctions", Proceeding of The IEEE, Vol. 91, No. 5, May 2003.
7. W. Zhao et al, "Integration of Spin-RAM technology in FPGA circuits", ICSICT, 2006.
8. W. Xu et al,"Spin-Transfer Torque Magnetoresistive Content Addressable Memory (CAM) Cell Structure Design with Enhanced Search Noise Margin",ISCAS, 2008.
9. Z. Diao et al, "Spin-transfer torque switching in magnetic tunnel junction and spin-tansfer torque random access memory", Journal of Physics: Condensed Matter, vol. 19, 165209, April 2007.
10. J. Cong and Y. Ding,"FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table based FPGA Designs," IEEE Trans. on CAD, Vol. 13, No. 1, pp. 1-12, Jan. 1994.
11. J.W. Tschanz et al, "Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors", JSSCC, 2003.
12. S. Bhunia et al,"A Novel Synthesis Approach for Active Leakage Power Reduction Using Dynamic Supply Gating", DAC, 2005.
13. L. Leinweber and S. Bhunia, "Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction", DATE, 2008.