-
1
-
-
0026676975
-
Design for testability: Using scan path techniques for path-delay test and measurement
-
B. I. Dervisoglu and G. E. Stong, "Design for testability: using scan path techniques for path-delay test and measurement", Proc. of Int. Test Conf., 1991, pp. 365-374.
-
Proc. of Int. Test Conf., 1991
, pp. 365-374
-
-
Dervisoglu, B.I.1
Stong, G.E.2
-
2
-
-
0002129847
-
A Distributed BIST Control Scheme for Complex VLSI Devices
-
Y. Zorian, "A Distributed BIST Control Scheme for Complex VLSI Devices," Proc. of VLSI Testing Symposium, pp. 4-9, 1993.
-
(1993)
Proc. Of VLSI Testing Symposium
, pp. 4-9
-
-
Zorian, Y.1
-
3
-
-
0036443053
-
Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST
-
S. Wang, "Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST," International Test Conference, 2002, pp. 834-843.
-
International Test Conference, 2002
, pp. 834-843
-
-
Wang, S.1
-
6
-
-
0032306939
-
Native model functional test generation for processors with applications to self test and design validation
-
J. Shen and J. A. Abraham, "Native model functional test generation for processors with applications to self test and design validation," Proc. Intl. Test Conf., Oct. 1998, pp.990-999
-
Proc. Intl. Test Conf., Oct. 1998
, pp. 990-999
-
-
Shen, J.1
Abraham, J.A.2
-
8
-
-
0036446080
-
FRITS - A microprocessor functional BIST method
-
P. Parvathala, K. Maneparambil and W. Lindsay, "FRITS - A microprocessor functional BIST method," Proc. Intl Test Conf., Oct 2002, pp.590-598.
-
Proc. Intl Test Conf., Oct 2002
, pp. 590-598
-
-
Parvathala, P.1
Maneparambil, K.2
Lindsay, W.3
-
10
-
-
0035272504
-
Software-Based self-testing methodology for processor cores
-
March
-
L. Chen and S. Dey, "Software-Based self-testing methodology for processor cores," IEEE Trans. Computer-Aided Design, vol.20, no.3, March 2001, pp.369-380.
-
(2001)
IEEE Trans. Computer-Aided Design
, vol.20
, Issue.3
, pp. 369-380
-
-
Chen, L.1
Dey, S.2
-
14
-
-
0034482483
-
Test program synthesis for path delay faults in microprocessor cores
-
W. -C. Lai, A. Krstic and K.-T. Cheng, "Test program synthesis for path delay faults in microprocessor cores," Proc. Intl. Test Conf., Oct. 2000, pp.1080-1089
-
Proc. Intl. Test Conf., Oct. 2000
, pp. 1080-1089
-
-
Lai, W.C.1
Krstic, A.2
Cheng, K.-T.3
-
15
-
-
0042134725
-
A Scalable Software-Based Self-Test Methodology for Programmable Processors
-
L. Chen, S. Ravi, A. Raghunathan and S. Dey, "A Scalable Software-Based Self-Test Methodology for Programmable Processors," Proc. Design Automation Conference, June 2003, pp.548-553.
-
Proc. Design Automation Conference, June 2003
, pp. 548-553
-
-
Chen, L.1
Ravi, S.2
Raghunathan, A.3
Dey, S.4
-
17
-
-
0031384267
-
A Novel Functional Test Generation Method for Processors using Commerical ATPG
-
R. Tupuri and J. Abraham, "A Novel Functional Test Generation Method for Processors using Commerical ATPG," Proc. Intl. Test Conference, Nov. 1997, pp.743-752
-
Proc. Intl. Test Conference, Nov. 1997
, pp. 743-752
-
-
Tupuri, R.1
Abraham, J.2
-
18
-
-
0142246956
-
ATPG for Crosstalk using Hybrid Structural SAT
-
X. Bai, S. Dey and A. Krstic, "ATPG for Crosstalk using Hybrid Structural SAT", proc. Intl. Test Conference, Oct. 2003, pp, 112-121.
-
Proc. Intl. Test Conference, Oct. 2003
, pp. 112-121
-
-
Bai, X.1
Dey, S.2
Krstic, A.3
-
19
-
-
84944326567
-
-
Mentor Graphics Corp.
-
LeonardoSpectrum™, Mentor Graphics Corp.
-
LeonardoSpectrum™
-
-
-
20
-
-
84944314970
-
-
Mentor Graphics Corp.
-
IC Station®, Mentor Graphics Corp.
-
IC Station®
-
-
-
21
-
-
84944337468
-
-
Mentor Graphics Corp.
-
xCalibre®, Mentor Graphics Corp.
-
xCalibre®
-
-
-
22
-
-
67649647250
-
Noise-Aware Driver Modeling
-
X. Bai, R. Chandra, S. Dey and P.V. Srinivas, "Noise-Aware Driver Modeling," Proc. of International Symposium on Quality Electronic Design, March 2003, pp.177-182.
-
Proc. of International Symposium on Quality Electronic Design, March 2003
, pp. 177-182
-
-
Bai, X.1
Chandra, R.2
Dey, S.3
Srinivas, P.V.4
|