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Volumn , Issue , 2003, Pages 112-121

HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; BOOLEAN ALGEBRA; CAPACITANCE; SPURIOUS SIGNAL NOISE; TUNING; VECTORS;

EID: 0142246956     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (23)

References (29)
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    • 0032316471 scopus 로고    scopus 로고
    • Automatic test pattern generation for crosstalk glitches in digital circuits
    • K. T. Lee, C. Nordquist and J. A. Abraham, "Automatic test pattern generation for crosstalk glitches in digital circuits," Proc. of VLSI Test Symposium, pp. 34-39, 1998.
    • (1998) Proc. of VLSI Test Symposium , pp. 34-39
    • Lee, K.T.1    Nordquist, C.2    Abraham, J.A.3
  • 8
    • 0032306411 scopus 로고    scopus 로고
    • Test generation in VLSI circuits for crosstalk noise
    • W. Y. Chen, S. K. Gupta and M.A. breuer, "Test generation in VLSI circuits for crosstalk noise," Proc. Int'l Test Conf., pp. 641-650, 1998.
    • (1998) Proc. Int'l Test Conf. , pp. 641-650
    • Chen, W.Y.1    Gupta, S.K.2    Breuer, M.A.3
  • 9
    • 0033316674 scopus 로고    scopus 로고
    • Test generation for crosstalk-induced delay in integrated circuits
    • W. Y. Chen, S. K. Gupta and M. A. Breuer, "Test generation for crosstalk-induced delay in integrated circuits," Proc. Int'l Test Conf., pp. 191-200, 1999.
    • (1999) Proc. Int'l Test Conf. , pp. 191-200
    • Chen, W.Y.1    Gupta, S.K.2    Breuer, M.A.3
  • 10
    • 0142206125 scopus 로고    scopus 로고
    • Timed Test Generation for Crosstalk Switch Failures in Domino CMOS Circuits
    • R. Kundu and R. D. Blanton, "Timed Test Generation for Crosstalk Switch Failures in Domino CMOS Circuits," Proc. of VLSI Test Symposium, pp. 379-385 2001.
    • (2001) Proc. of VLSI Test Symposium , pp. 379-385
    • Kundu, R.1    Blanton, R.D.2
  • 11
    • 0036446483 scopus 로고    scopus 로고
    • Testing Cross-Talk Induced Delay Faults in static CMOS circuit Though Dynamic Timing Analysis
    • Oct.
    • B. C Paul, K. Roy, "Testing Cross-Talk Induced Delay Faults in static CMOS circuit Though Dynamic Timing Analysis," International Test Conference, pp. 384-390, Oct. 2002.
    • (2002) International Test Conference , pp. 384-390
    • Paul, B.C.1    Roy, K.2
  • 15
    • 0023558527 scopus 로고
    • SOCRATES: A highly efficient automatic test pattern generation system
    • Schulz M., Trischler E., Sarfert T., "SOCRATES: A highly efficient automatic test pattern generation system," Proc. Intl. Test Conf., pp. 1016-1026, 1987.
    • (1987) Proc. Intl. Test Conf. , pp. 1016-1026
    • Schulz, M.1    Trischler, E.2    Sarfert, T.3
  • 21
    • 0019543877 scopus 로고
    • An implicit enumeration algorithm to generate tests for combinational logic circuits
    • Mar.
    • P. Goel, "An implicit enumeration algorithm to generate tests for combinational logic circuits," IEEE Trans. Comput., Vol. C-30, pp. 215-222, Mar. 1981.
    • (1981) IEEE Trans. Comput. , vol.C-30 , pp. 215-222
    • Goel, P.1
  • 27
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    • LeonardoSpectrum™, Mentor Graphics Corp
    • LeonardoSpectrum™, Mentor Graphics Corp.
  • 28
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    • IC Station®, Mentor Graphics Corp.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.