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Volumn , Issue , 2007, Pages 613-618

An RLDRAM II implementation of a 10Gps shared packet buffer for network processing

Author keywords

[No Author keywords available]

Indexed keywords

LOW COSTS; MEMORY ADDRESSING; NETWORK PROCESSING; PACKET DATA; THROUGHPUT RATES;

EID: 50949108937     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/AHS.2007.30     Document Type: Conference Paper
Times cited : (10)

References (11)
  • 1
    • 48149097211 scopus 로고    scopus 로고
    • Worldwide Bandwidth End-User Forecast and Analysis, 2003-2007
    • International Data Group IDG
    • International Data Group (IDG), "Worldwide Bandwidth End-User Forecast and Analysis, 2003-2007: More is Still Not Enough," 2003.
    • (2003) More is Still Not Enough
  • 2
    • 50949091107 scopus 로고    scopus 로고
    • http://www.micron.com/products/dram/rldram/
  • 3
    • 30844458064 scopus 로고
    • A shared buffer memory switch for an ATM exchange
    • H. Kuwahara, "A shared buffer memory switch for an ATM exchange," IEEE GLOBECOM, 1989.
    • (1989) IEEE GLOBECOM
    • Kuwahara, H.1
  • 4
    • 0023438266 scopus 로고
    • A Broadband Packet Switch for Integrated Transport
    • Oct
    • J.Y. Hui, E. Arthurs "A Broadband Packet Switch for Integrated Transport" IEEE Journal Selected Areas in Communications, Vol.5, No. 8, pp 1264-1273, Oct. 1988.
    • (1988) IEEE Journal Selected Areas in Communications , vol.5 , Issue.8 , pp. 1264-1273
    • Hui, J.Y.1    Arthurs, E.2
  • 5
    • 0034499316 scopus 로고    scopus 로고
    • A combined input and output queued packet switched system based on PRIZMA switch on a chip technology
    • Dec
    • C. Minkenberg, T. Engbersen, "A combined input and output queued packet switched system based on PRIZMA switch on a chip technology," IEEE Communications Magazine, Dec. 2000.
    • (2000) IEEE Communications Magazine
    • Minkenberg, C.1    Engbersen, T.2
  • 6
    • 20844434131 scopus 로고
    • Queuing in high-performance packet switching
    • M. Hluchyj and M. Karol, "Queuing in high-performance packet switching," IEEE Journal, SAC-5, 1987.
    • (1987) IEEE Journal , vol.SAC-5
    • Hluchyj, M.1    Karol, M.2
  • 7
    • 0346752335 scopus 로고    scopus 로고
    • Gigabit Ethernet switches using a shared buffer architecture
    • M. Lau, S. Shieh, "Gigabit Ethernet switches using a shared buffer architecture," IEEE Communications Magazine, 2003.
    • (2003) IEEE Communications Magazine
    • Lau, M.1    Shieh, S.2
  • 8
    • 50949133577 scopus 로고
    • CAM-Based single-chip shared buffer ATM switch
    • K. J. Schultz and P. G. Gulak, "CAM-Based single-chip shared buffer ATM switch", IEEE ICC'94, 1994.
    • (1994) IEEE ICC'94
    • Schultz, K.J.1    Gulak, P.G.2
  • 10
    • 0027612043 scopus 로고
    • A Generalized Processor Sharing Approach to Flow Control in Integrated Services Networks: The Single Node Case
    • June
    • A. Parekh and R. Gallager, "A Generalized Processor Sharing Approach to Flow Control in Integrated Services Networks: The Single Node Case," ACM/IEEE Trans. Networking, vol. 1, June 1993, pp. 344-357.
    • (1993) ACM/IEEE Trans. Networking , vol.1 , pp. 344-357
    • Parekh, A.1    Gallager, R.2
  • 11
    • 85027144790 scopus 로고    scopus 로고
    • J.W. Shim, G.J. Jeong, M.K. Lee, FPGA implementation of a scalable shared buffer ATM switch, ATM, June 1998.
    • J.W. Shim, G.J. Jeong, M.K. Lee, "FPGA implementation of a scalable shared buffer ATM switch," ATM, June 1998.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.