A 2.8 GS/s 44.6 mW time-interleaved ADC achieving 50.9 dB SNDR and 3 dB effective resolution bandwidth of 1.5 GHz in 65 nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 48, Issue 4, 2013, Pages 971-982

  Stepanovic, Dušan ^a,b   Nikolic, Borivoje ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b AGILENT TECHNOLOGIES   (United States)

Author keywords

A D; ADC; background; calibration; CMOS; converters; linearity; SAR; time interleaved; timing

Indexed keywords

A/D; ADC; BACKGROUND; LINEARITY; SAR; TIME-INTERLEAVED; TIMING;

CALIBRATION; CAPACITORS; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; TORQUE CONVERTERS;

ANALOG TO DIGITAL CONVERSION;

EID: 84875697779     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2013.2239005     Document Type: Article

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