A 5.37mW 10b 200MS/s dual-path pipelined ADC

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 462-463

  Chai, Yun ^a   Wu, Jieh Tsorng ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DC GAIN; DUAL PATH; LARGE POWER; LOW-POWER DISSIPATION; PIPELINED ADCS; RESIDUE AMPLIFICATION; SAMPLE-AND-HOLD; SAMPLING RATES; SIGNAL RANGE; SLOW SPEED; SWITCHED CAPACITOR;

AMPLIFICATION;

EID: 84860665722     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6177091     Document Type: Conference Paper

References (3)

1. Y.-C. Huang and T.-C. Lee, "A 10b 100MS/s 4.5mW Pipelined ADC with a Time Sharing Technique," ISSCC Dig. Tech. Papers, pp. 300-301, Feb. 2010.
2. J. Mulder, et al., "An 800MS/s Dual-Residue Pipeline ADC in 40nm CMOS,"ISSCC Dig. Tech. Papers, pp. 184-185, Feb. 2011.
3. S. Ouzounov, et al., "A 1.2V 121-Mode CT ΔΣ Modulator for Wireless Receivers in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 242-243, Feb. 2007.