A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 470-471

  Malki, Badr ^a,b   Yamamoto, Takaya ^c   Verbruggen, Bob ^a   Wambacq, Piet ^a,b   Craninckx, Jan ^a  

^a IMEC   (Belgium)

^b VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

^c RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE DYNAMIC RANGE; INNOVATIVE SYSTEMS; LOW-POWER CONSUMPTION; RAIL-TO-RAIL; SAMPLING CAPACITOR; SAR ADC; VARIABLE GAIN AMPLIFIERS; WIRELESS RECEIVERS; WIRELESS SYSTEMS;

EID: 84860673868     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6177095     Document Type: Conference Paper

References (5)

1. J. Craninckx and G. Van der Plas, "A 65fJ/Conversion-Step, 0-to-50MS/s 0-to-0.7mW 9b Charge Sharing SAR ADC in 90nm Digital CMOS", ISSCC Dig. Tech. Papers, pp. 246-247, Feb. 2007.
2. V. Giannini, et al., "An 820μW 9b 40MS/s Noise Tolerant Dynamic SAR ADC in 90nm Digital CMOS", ISSCC Dig. Tech. Papers, pp. 238-239, Feb. 2008.
3. L. Carley and T. Mukherjee, "High-Speed Low-Power Integrating CMOS Sample-and-Hold Amplifier Architecture" Proc. IEEE Custom Integrated Circuits Conf., pp. 543-546, 1995.
4. S. Ranganathan and Y. Tsividis, "Discrete-Time Parametric Amplification Based on a Three-Terminal MOS Varactor: Analysis and Experimental Results", IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2087-2093, Dec. 2003.
5. M. Miyahara, et al., "A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs," IEEE Asian Solid-State Circuits Conf., pp. 269-272, Nov. 2008.