A 480 mW 2.6 GS/s 10b time-interleaved ADC with 48.5 dB SNDR up to Nyquist in 65 nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 12, 2011, Pages 2821-2833

  Doris, Kostas ^a   Janssen, Erwin ^a   Nani, Claudio ^a   Zanikopoulos, Athon ^a   Van Der Weide, Gerard ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

Author keywords

Analog to digital converter; calibration; clock jitter; direct sampling receiver; Nyquist converter; successive approximation register; time interleaving; timing skew; track and hold

Indexed keywords

ANALOG TO DIGITAL CONVERTERS; CLOCK-JITTER; DIRECT SAMPLING RECEIVER; NYQUIST CONVERTERS; SUCCESSIVE APPROXIMATION REGISTER; TIME-INTERLEAVING; TIMING SKEW; TRACK-AND-HOLD;

APPROXIMATION THEORY; CALIBRATION; CLOCKS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CONVERTERS; TIMING JITTER;

ANALOG TO DIGITAL CONVERSION;

EID: 82155166398     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2164961     Document Type: Conference Paper

References (41)

1. E. Janssen et al., "A direct sampling multi-channel receiver for DOCSIS 3.0 in 65 nm," in Proc. IEEE Symp. VLSI Circuits, 2011.
2. F. Gatta et al., "An embedded 65 nm CMOS baseband IQ 48 MHz-1 GHz dual tuner for DOCSIS 3.0," IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3511-3525, Dec. 2009.
3. D. Drexelmayr, "A 6b 600 MHz 10 mW ADC array in digital 90 nm CMOS," in IEEE ISSCC Dig., 2004, pp. 264-265.
4. P. Schvan et al., "A 24 GS/s 6b ADC in 90 nm CMOS," in IEEE ISSCC Dig., 2008, pp. 544-545.
5. D. Greshishchev et al., "A 40 GS/s 6b ADC in 65 nm CMOS," in IEEE ISSCC Dig., 2010, pp. 390-391.
6. S. M. Louwsma et al., "A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13 μm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 778-786, Apr. 2008.
7. E. Alpman et al., "A 1.1 V 50 mW 2.5 GS/s 7b time-interleaved C-2C SAR ADC in 45 nm LP digital CMOS," in IEEE ISSCC Dig., 2009, pp. 76-77, 77a.
8. W. Liu et al., "A 600 MS/s 30 mW 0.13 um CMOS ADC array achieving over 60 dB SFDR with adaptive digital equalization," in IEEE ISSCC Dig., 2009, pp. 82-83.
9. M. Van Elzakker et al., "A 10-bit charge-redistribution ADC consuming 1.9 μW at 1 MS/s," IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010.
10. P. Harpe et al., "A30 fJ/conversion-step 8b 0-to-10 MS/s asynchronous SAR ADC in 90 nm CMOS," in IEEE ISSCC Dig., 2010, pp. 387-389.
11. M. Hesener et al., "A 14b 40 MS/s redundant SAR ADC with 480 MHz clock in 0.13 μm CMOS," in IEEE ISSCC Dig., 2007, pp. 248-249.
12. W. Liu et al., "A 12b 22.5/45 MS/s 3.0 mW 0.059 mm CMOS SAR ADC achieving over 90 dB SFDR," in IEEE ISSCC Dig., 2010, pp. 380-381.
13. C. C. Liu et al., "A 10b 100 MS/s 1.13 mW SAR ADC with binaryscaled error compensation," in IEEE ISSCC Dig., 2010, pp. 386-387.
14. ADC12D1x00 12-bit ADC Family. National Semiconductors website
15. K. Doris et al., "A 480 mW 2.6 GS/s 10b 65 nm time-interleaved ADC with 48.5 dB SNDR up to Nyquist," in IEEE ISSCC Dig., 2011, pp. 180-182.
16. N. Kurosawa et al., "Explicit analysis of channel mismatch effects in time-interleaved ADC systems," IEEE Trans. Circuits Syst. I, Fund. Theory Applicat., vol. 48, no. 3, pp. 261-271, Mar. 2001.
17. C. Vogel, "The impact of combined channel mismatch effects in timeinterleaved ADCs," IEEE Trans. Instrum. Meas., vol. 54, no. 1, pp. 415-427, 2005.
18. A. Balakrishnan, "On the problem of time jitter in sampling," IRE Trans. Inf. Theory, vol. 8, no. 3, pp. 226-236, 1962.
19. K. Doris, "High-Speed D/A converters: From analysis and synthesis concepts to IC implementation," Ph.D. dissertation, Technical University Eindhoven, Eindhoven, The Netherlands, 2004.
20. K. Poulton et al., "A 20 GS/s 8b ADC with a 1 MB memory in 0.18 um CMOS," in IEEE ISSCC Dig., 2003, pp. 318-319.
21. R. C. Taft et al., "A 1.8 V 1.0 GS/s 10b self-calibrating unified-foldinginterpolating ADC with 9.1 ENOB at Nyquist frequency," in IEEE ISSCC Dig., 2009, pp. 77-78, 79a.
22. R. Payne et al., "A 12b 1 GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC," in IEEE ISSCC Dig., 2011, pp. 182-184.
23. H. Van De Vel et al., "A 1.2-V 250-mW 14-b 100-MS/s digitally calibrated pipeline ADC in 90-nm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1047-1056, Apr. 2009.
24. A. M. A. Ali et al., "A 16-bit 250-MS/s IF sampling pipelined ADC with background calibration," IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2602-2612, Dec. 2010.
25. B. Verbruggen et al., "A 2.6 mW 6b 2.2 GS/s 4-times interleaved fully dynamic pipelined ADC in 40 nm digital CMOS," in IEEE ISSCC Dig., 2010, pp. 296-297.
26. S. Gupta et al., "A 1 GS/s 11b time-interleaved ADC with 55-dB SNDR, 250 mW power realized by a high bandwidth scalable time-interleaved architecture," IEEE J. Solid-State Circuits, vol. 41, pp. 2650-2657, Dec. 2006.
27. A. Nazemi et al., "A 10.3 Gs/s 6 bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90 nm CMOS," in Proc. IEEE Symp. VLSI Circuits, 2008, pp. 18-19.
28. B. Murmann, "Low-power pipelined A/D conversion," in Proc. 20th Workshop on Advances in Analog Circuit Design (AACD), Apr. 2011.
29. M. Gustavsson and N. N. Tan, "A global passive sampling technique for high-speed switched-capacitor time-interleaved ADCs," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 9, pp. 821-831, Sep. 2000.
30. B. P. Ginsburg and A. P. Chandrakasan, "Highly interleaved 5-bit, 250-MSample/s, 1.2-mW ADC with redundant channels in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2641-2650, Dec. 2008.
31. A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, May 1999.
32. C.-C. Hsu et al., "An 11b 800 MS/s time-interleaved ADC with digital background calibration," in IEEE ISSCC Dig., 2007, pp. 464-465.
33. C.-C. Hsu et al., "A 7b 1.1 GS/s reconfigurable time-interleaved ADC in 90 nm CMOS," in Proc. IEEE Symp. VLSI Circuits, 2007, pp. 66-67.
34. R. C. Taft et al., "A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2107-2115, Dec. 2004.
35. X. Jiang and M.-C. F. Chang, "A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging," IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 532-535, Feb. 2005.
36. Z. Cao, S. Yan, and Y. Li, "A 32 mW 1.25 GS/s 6b 2b/step SAR ADC in 0.13 μm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 862-873, Mar. 2009.
37. B. Razavi, Principles of Data Conversion System Design. New York: IEEE Press, 1995, vol. 126.
38. T. Kobayashi et al., "A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architectures," IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 523-527, Apr. 1993.
39. Data over cable service interface specifications DOCSIS3.0, Cable-Labs, Physical Layer Specification CM-SP-PHYv3.0-I09-101008.
40. J. Elbornsson, F. Gustafsson, and J.-E. Eklund, "Analysis of mismatch noise in randomly interleaved ADC system," in Proc. IEEE ICASSP, 2003, vol. 6, pp. 277-280.
41. [Online]. Available: Http://www.national.com/assets/en/other/national- adc12d1x00-product-brief.pdf