A 1.1V 50mW 2.5GS/s 7b time-interleaved C-2C SAR ADC in 45nm LP digital CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages

  Alpman, Erkan ^a,b   Lakdawala, Hasnain ^a   Carley, L Richard ^b   Soumyanath, K ^a  

^a INTEL CORPORATION   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349289826     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977315     Document Type: Conference Paper

References (4)

1. P. Schvan, et al., "A 24GS/s 6b ADC in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 544-545, Feb. 2008.
2. S. V. Iyer et al., "A 0.5mm2 Integrated Capacitive Vibration Sensor with Sub-10 zF/rt- Hz Noise Floor," IEEE Custom Integrated Circuits Conf., pp. 93-96, Sept. 2005.
3. S. M. Chen and R. W. Brodersen, "A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-μ m CMOS," IEEE J. Solid-State Circuits, vol.41, no.12, pp. 2669-2680, Dec. 2006.
4. S. M. Jamal, et al., "Calibration of Sample-Time Error in a Two-Channel Time- Interleaved Analog-to-Digital Converter," IEEE Trans. Circuits and Systems-I, vol.51, no.1, pp. 130-139, Jan. 2004.